Report generated on 07-May-2025 at 00:35:23 by pytest-html v3.2.0
1063 tests ran in 28.82 seconds.
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521 passed, 0 skipped, 542 failed, 0 errors, 0 expected failures, 0 unexpected passes| Result | Test | TIDL Subgraphs | Complete TIDL Offload | Duration | Links |
|---|---|---|---|---|---|
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| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_510] | 1 | False | 0.29 | |
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[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_510' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_510', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479321 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ad55fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.44065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.44100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.44140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.44165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.44200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.44227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.44254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.44283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.44307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.44331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.44354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.44380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.44407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.44436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.44462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.44491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.44518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.44541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.44573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.44597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.44619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.44648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.44669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.44690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.44722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.44749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.44774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.44800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.44826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.44850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.44886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.44909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.44942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.44976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.45002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.45035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.45071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.45093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.45119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.45152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.45177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.45179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.45182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.917530086 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,30,43,4} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,30,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_439] | 1 | False | 0.28 | |
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[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_439' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_439', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479312 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde21bb70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.905690505 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,22,9,2} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,22,9,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_455] | 1 | False | 0.31 | |
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[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_455' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_455', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479314 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f104360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.986585759 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,11,22,2} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,11,22,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1052] | 1 | True | 0.30 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1052' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1052', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479313 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe61a700 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3551s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21701413 bytes MEM: Free's : 26 free's of 21701413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (160, 12, 9, 13) got (2, 12, 9, 13) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_835] | 1 | False | 0.31 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_835' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_835', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479319 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17971c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.975110698 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,1,11} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_192] | 1 | False | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_192' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_192', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-1' pid=479320 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508072d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_192/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_903] | 1 | False | 0.28 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_903' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_903', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479331 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7a1ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2683s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.904859706 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{138,2,5} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{138,2,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_221] | 1 | False | 0.22 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_221' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_221', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-1' pid=479318 parent=477852 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa24a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_221/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_768] | 1 | False | 0.28 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_768' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_768', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479323 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3666370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.888483669 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,11} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_410] | 1 | False | 0.27 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_410' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_410', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479328 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59391cecf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.862948048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,2,11,22} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,2,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_550] | 1 | False | 0.28 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_550' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_550', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479329 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a14cf10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1696s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.861191915 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,4,30,4} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,4,30,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_308] | 1 | False | 0.31 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_308' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_308', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-1' pid=479316 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e87e0f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_308/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1031] | 1 | False | 0.22 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1031' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1031', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479315 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122c50a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.847081137 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{84,4,11,4} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{84,4,11,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1036] | 1 | False | 0.26 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1036' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1036', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479317 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e14360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.918461278 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,66,14,4} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,66,14,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_277] | 1 | False | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_277' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_277', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-1' pid=479324 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68699a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_277/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_549] | 1 | False | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_549' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_549', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479326 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9289bee10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.922839543 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,4,4,30} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,4,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_117] | 1 | False | 0.28 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_117' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_117', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=479327 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376be59370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.38360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.38386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.38406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.38421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.38436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.38437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.38440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:08.883181242 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,3,4,80} Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,3,4,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_689] | 1 | False | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_689' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_689', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-2' pid=480713 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740ce31c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_689/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_279] | 1 | False | 0.25 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_279' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_279', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-2' pid=480802 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51fb4280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_279/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_742] | 1 | False | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_742' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_742', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-2' pid=480804 parent=478387 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a410acf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_742/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_804] | 1 | False | 0.22 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_804' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_804', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=480852 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c3ee6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.149296705 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,1,11,11} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,1,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_429] | 1 | False | 0.24 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_429' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_429', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=480933 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582507fcf520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2084s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.184534899 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,22,11} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,22,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_21] | 1 | False | 0.18 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_21' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_21', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=481055 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf8f980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.210746078 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2048} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2048} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_468] | 1 | False | 0.15 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_468' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_468', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=481145 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67c6360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1770s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1772s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.230852771 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,11,2,9} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,11,2,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1025] | 1 | False | 0.19 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1025' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1025', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=481162 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59393025f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.267146522 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,5,6,2} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,5,6,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_301] | 1 | False | 0.30 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_301' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_301', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-2' pid=481485 parent=478151 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179b6140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_301/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_886] | 1 | False | 0.33 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_886' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_886', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=481569 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa710a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.536139067 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,11,16,1} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,11,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_157] | 1 | False | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_157' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_157', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=481570 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfdaf500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_157/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_593] | 1 | False | 0.31 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_593' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_593', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=481643 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825082a1fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.572397160 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,12,4,43} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,12,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_488] | 1 | False | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_488' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_488', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=481645 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27cedc70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.462465080 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,2,9,11} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,2,9,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_443] | 1 | False | 0.25 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_443' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_443', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=481644 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35c00f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.452480166 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,9,11,2} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,9,11,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_524] | 1 | False | 0.27 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_524' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_524', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=481710 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59394e83d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4828s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.560167000 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,43,4,12} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,43,4,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_922] | 1 | False | 0.20 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_922' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_922', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=481932 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c433920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.555607575 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,1,6,5} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,1,6,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_517] | 1 | False | 0.17 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_517' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_517', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=482056 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f419980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.544630398 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,43,12,30} Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,43,12,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_659] | 1 | False | 0.12 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_659' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_659', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-3' pid=482232 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9288254c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_659/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_695] | 1 | False | 0.14 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_695' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_695', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-3' pid=482315 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d27db0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_695/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_639] | 1 | False | 0.22 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_639' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_639', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-2' pid=482472 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde34ceb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_639/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_574] | 1 | False | 0.18 | |
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[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_574' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_574', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=482561 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe933020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11250s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.720354299 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,4,30,12} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,4,30,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_489] | 1 | False | 0.38 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_489' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_489', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=482628 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d57a00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.30502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.30546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.30566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.30594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.30623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.30647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.30667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.30688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.30708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.30730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.30752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.30771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.30796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.30819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.30841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.30862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.30885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.30904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.30923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.30945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.30966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.30989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.31011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.31033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.31052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.31072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.31093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.31116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.31137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.31158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.31182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.31200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.31224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.31242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.31263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.31282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.31308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.31329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.31351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.31372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.31396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.31397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.31400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.894158574 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,2,11,9} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,2,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1022] | 1 | False | 0.37 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1022' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1022', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-4' pid=482662 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68ba750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.29028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.29058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.29085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.29105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.29131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.29150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.29171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.29193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.29211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.29238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.29255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.29273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.29302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.29329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.29346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.29371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.29392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.29409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.29441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.29463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.29483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.29511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.29529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.29546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.29573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.29593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.29615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.29636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.29653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.29670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.29699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.29716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.29733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.29754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.29775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.29801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.29833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.29853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.29871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.29897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.29918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.29920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.29922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.879135891 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,6,2,5} Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,6,2,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_975] | 1 | False | 0.21 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_975' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_975', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-4' pid=482664 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92882bae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1800s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.799002363 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,1,6,23,2} Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,1,6,23,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_758] | 1 | False | 0.20 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_758' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_758', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-3' pid=482688 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51ff9100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_758/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_538] | 1 | False | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_538' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_538', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-3' pid=482779 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4333650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.892458208 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,4,43,30} Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,4,43,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_880] | 1 | False | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_880' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_880', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-4' pid=482963 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080c4f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5269s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.778115547 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,11,1,1} Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,11,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_214] | 1 | False | 0.23 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_214' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_214', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-3' pid=483441 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122f1560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_214/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_943] | 1 | False | 0.38 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_943' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_943', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-4' pid=483358 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e20920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.34124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.34163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.34194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.34217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.34245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.34265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.34289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.34311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.34333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.34353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.34376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.34397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.34418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.34442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.34466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.34488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.34511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.34529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.34551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.34573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.34595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.34620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.34641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.34663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.34683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.34711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.34732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.34750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.34776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.34795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.34821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.34842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.34864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.34886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.34918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.34936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.34963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.34986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.35008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.35031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.35067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.35068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.35071s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.932099754 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,23,2,1,5} Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,23,2,1,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_755] | 1 | False | 0.17 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_755' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_755', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-4' pid=483399 parent=477728 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939307230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_755/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_797] | 1 | False | 0.34 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_797' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_797', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=483718 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27303de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1940s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1943s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:09.907097857 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,1,11,11} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,1,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_225] | 1 | False | 0.25 | |
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[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_225' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_225', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-4' pid=483765 parent=477740 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe753e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_225/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_150] | 1 | False | 0.36 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_150' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_150', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-3' pid=484222 parent=477734 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde350dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1734s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.074392809 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,128,8,2} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_470] | 1 | False | 0.24 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_470' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_470', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-4' pid=484156 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35c74d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1700s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.023691180 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,9,11,11} Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,9,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_403] | 1 | False | 0.17 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_403' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_403', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=484265 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376beac250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.047582951 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,2,22,11,11} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,2,22,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_651] | 1 | False | 0.34 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_651' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_651', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-4' pid=484290 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51ffcde0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_651/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_212] | 1 | False | 0.17 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_212' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_212', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-5' pid=484289 parent=477728 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939309c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_212/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_350] | 1 | False | 0.27 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_350' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_350', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-4' pid=484354 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122f47d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_350/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_262] | 1 | False | 0.24 | |
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[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_262' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_262', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-5' pid=484508 parent=477744 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c438600 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_262/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_977] | 1 | False | 0.27 | |
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[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_977' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_977', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=484711 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa771d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.136375324 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,1,23,6,2} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,1,23,6,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_743] | 1 | False | 0.21 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_743' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_743', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-4' pid=484710 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abbe4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_743/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_660] | 1 | False | 0.20 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_660' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_660', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-5' pid=484909 parent=478383 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfdf8e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_660/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_491] | 1 | False | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_491' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_491', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=484999 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe66b0d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.261561600 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,9,11,2} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,9,11,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_59] | 1 | False | 0.19 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_59' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_59', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=485205 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d37ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.253458046 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{8,64,64} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{8,64,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_285] | 1 | False | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_285' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_285', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-5' pid=485455 parent=477985 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36b32c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_285/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_954] | 1 | False | 0.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_954' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_954', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=485616 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a415a330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.326106881 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,6,23,1} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,6,23,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_452] | 1 | False | 0.20 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_452' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_452', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=485720 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871220b9c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1698s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.348146821 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,11,22} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_824] | 1 | False | 0.25 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_824' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_824', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-6' pid=485868 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe00530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1523s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.376456054 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,11,16} Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,11,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_681] | 1 | False | 0.23 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_681' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_681', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-5' pid=485869 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abc1320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_681/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_866] | 1 | False | 0.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_866' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_866', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=485936 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f243c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.420260788 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,16,1,1} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,16,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_186] | 1 | False | 0.24 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_186' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_186', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=485938 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51ffd3a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_186/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_219] | 1 | False | 0.24 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_219' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_219', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-4' pid=485964 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde352040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_219/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_907] | 1 | False | 0.31 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_907' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_907', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-6' pid=485962 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27349850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.26514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.26544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.26578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.26602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.26632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.26655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.26675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.26797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.26824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.26850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.26871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.26895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.26917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.26935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.26962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.26987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.523082979 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,6,5,1,23} Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,6,5,1,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_466] | 1 | False | 0.22 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_466' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_466', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=485987 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939226710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.445626539 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,9,2,11} Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,9,2,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_259] | 1 | False | 0.35 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_259' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_259', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-7' pid=486136 parent=477748 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf9a140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_259/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_416] | 1 | False | 0.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_416' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_416', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-6' pid=486400 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740c46c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.517145063 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,22,2,11,11} Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,22,2,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_673] | 1 | False | 0.28 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_673' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_673', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-7' pid=486571 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928831160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_673/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_342] | 1 | False | 0.27 | |
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[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_342' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_342', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-6' pid=486878 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68bcb40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_342/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_883] | 1 | False | 0.17 | |
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[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_883' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_883', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-6' pid=486877 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122fd770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.556177756 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,1,11} Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_661] | 1 | False | 0.21 | |
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[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_661' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_661', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-7' pid=487137 parent=478151 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179c3340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_661/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_916] | 1 | False | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_916' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_916', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-5' pid=487440 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7f0cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.717135223 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,1,6,23} Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,1,6,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_809] | 1 | False | 0.41 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_809' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_809', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-6' pid=487335 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52004260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19912s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.822100030 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,1,11} Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_95] | 1 | False | 0.22 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_95' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_95', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=487239 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939229e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.657171862 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{240,4,80} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{240,4,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1040] | 1 | True | 0.29 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1040' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1040', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=487780 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e44d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18865101 bytes MEM: Free's : 26 free's of 18865101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (924, 4, 4) got (4, 4, 4) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_828] | 1 | False | 0.30 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_828' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_828', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=487846 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712301ce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.789104161 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,1,11,11} Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,1,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_181] | 1 | False | 0.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_181' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_181', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=487996 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe75b980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_181/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1046] | 1 | False | 0.40 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1046' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1046', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=487995 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740c48cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9117s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.971884434 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{192,9,10,13} Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{192,9,10,13} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_18] | 1 | False | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_18' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_18', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=488260 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928834b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671725 bytes MEM: Free's : 26 free's of 18671725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.863244592 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,64} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1049] | 1 | True | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1049' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1049', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=488259 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4071c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21773773 bytes MEM: Free's : 26 free's of 21773773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (26, 864, 10) got (2, 864, 10) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_87] | 1 | False | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_87' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_87', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=488346 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb178d8fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.921490312 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,64,4,2} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,64,4,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_338] | 1 | False | 0.30 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_338' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_338', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-6' pid=488347 parent=477988 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7f2510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_338/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_134] | 1 | False | 0.31 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_134' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_134', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-9' pid=488483 parent=477728 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939317780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5225s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.017302288 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,8,128,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_92] | 1 | False | 0.28 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_92' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_92', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=488482 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35cf9a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:10.982545606 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{240,320} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{240,320} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_766] | 1 | False | 0.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_766' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_766', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=488789 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abc85c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1603s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1605s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.021680631 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{176,1,11} Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{176,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_917] | 1 | False | 0.45 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_917' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_917', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=488596 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe05620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.103451990 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,1,23,6} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,1,23,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_382] | 1 | False | 0.28 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_382' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_382', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=489018 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe675800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.009491958 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,11,9,22} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,11,9,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_741] | 1 | False | 0.22 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_741' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_741', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-7' pid=489172 parent=478585 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e4e8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_741/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1051] | 1 | True | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1051' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1051', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=489130 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d417b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21696973 bytes MEM: Free's : 26 free's of 21696973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (234, 8, 12, 10) got (2, 8, 12, 10) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_136] | 1 | False | 0.35 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_136' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_136', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-9' pid=489528 parent=478652 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928837ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1806s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.241497233 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,128,128,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_149] | 1 | False | 0.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_149' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_149', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-9' pid=489570 parent=478151 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179c80f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.117526411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,128,2,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_997] | 1 | False | 0.21 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_997' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_997', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=489876 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36c1cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.222102132 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,1,2,5,6} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,1,2,5,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_959] | 1 | False | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_959' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_959', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=490093 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abcbe70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.319058912 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,1,23,6} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,1,23,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_70] | 1 | False | 0.22 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_70' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_70', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-8' pid=490328 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d62cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.27044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.27071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.27099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.27122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.27149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.27177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.27197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.27220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.27240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.27262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.27285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27984s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.354777549 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,64,64,2} Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,64,64,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_815] | 1 | False | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_815' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_815', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=490491 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e34540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.301047736 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,1,11} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_792] | 1 | False | 0.34 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_792' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_792', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=490865 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe0ab70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.503108793 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,11,1} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_882] | 1 | False | 0.24 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_882' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_882', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=491022 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187123098d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9068s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.472415451 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,1,11,16} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,1,11,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_952] | 1 | False | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_952' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_952', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=491023 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa81b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.494199612 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,1,23,2,5} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,1,23,2,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_892] | 1 | False | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_892' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_892', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=491048 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c445a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.464667665 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,16,1} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_170] | 1 | False | 0.17 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_170' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_170', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=491050 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abcd4c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_170/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1003] | 1 | False | 0.25 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1003' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1003', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=491291 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfa4c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.513053867 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,6,23,5} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,6,23,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_425] | 1 | False | 0.21 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_425' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_425', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=491224 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f15ef00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.496995031 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,11,22,9} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,11,22,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_444] | 1 | False | 0.15 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_444' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_444', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=491416 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939234240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4500s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.515129275 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,11,2,9} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,11,2,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_628] | 1 | False | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_628' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_628', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-10' pid=491833 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92883c3e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_628/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_995] | 1 | False | 0.36 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_995' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_995', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=492148 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d3b800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.725422221 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,5,1,6,2} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,5,1,6,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_43] | 1 | False | 0.24 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_43' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_43', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=491958 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fc3d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.582150125 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,1,32} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,1,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_135] | 1 | False | 0.29 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_135' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_135', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-10' pid=492147 parent=477887 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273546e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.728067876 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,128,8,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1033] | 1 | False | 0.19 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1033' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1033', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=492227 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593933e7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.679077049 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{56,6,11,4} Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{56,6,11,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_246] | 1 | False | 0.26 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_246' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_246', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-11' pid=492373 parent=477740 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe769280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_246/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_421] | 1 | False | 0.39 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_421' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_421', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=492676 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb178e5970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.911153923 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,22,11,11,2} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,22,11,11,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_760] | 1 | False | 0.15 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_760' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_760', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=492628 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080d3350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3751s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.765175290 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1936} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1936} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_765] | 1 | False | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_765' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_765', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=492677 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfaa820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.798199157 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,121} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,121} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_395] | 1 | False | 0.31 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_395' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_395', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=492918 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c35c040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.923648742 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,22,11,11,9} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,22,11,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_558] | 1 | False | 0.19 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_558' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_558', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=492917 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d38aa8e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.829396169 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,30,43,12} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,30,43,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_564] | 1 | False | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_564' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_564', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=493119 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d2801bba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.860956277 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,30,43,4} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,30,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1007] | 1 | False | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1007' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1007', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=493077 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4167610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.921194939 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,23,5,6} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,23,5,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1028] | 1 | False | 0.26 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1028' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1028', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=493200 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939342b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.933718049 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,924,4} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,924,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1041] | 1 | True | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1041' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1041', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=493391 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080f0e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19515277 bytes MEM: Free's : 26 free's of 19515277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (6, 11, 56, 4) got (4, 6, 11, 56, 4) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_746] | 1 | False | 0.19 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_746' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_746', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-10' pid=493418 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5200bf20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_746/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_592] | 1 | False | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_592' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_592', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=493462 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27538fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:11.972800987 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,4,43,12} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,4,43,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_640] | 1 | False | 0.19 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_640' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_640', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-12' pid=493528 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92883f980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_640/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_8] | 1 | False | 0.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_8' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_8', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=493941 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d3d6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.079529721 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{24,8} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{24,8} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_705] | 1 | False | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_705' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_705', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-11' pid=494034 parent=478221 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f24ed20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_705/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_496] | 1 | False | 0.27 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_496' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_496', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=494270 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a434d190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1419s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.208272793 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,1440,43} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,1440,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_688] | 1 | False | 0.20 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_688' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_688', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-11' pid=494395 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871230a960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_688/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_739] | 1 | False | 0.14 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_739' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_739', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-12' pid=494397 parent=477737 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e3a660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_739/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_808] | 1 | False | 0.30 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_808' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_808', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=494422 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c44e610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.267140216 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,11,1} Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_586] | 1 | False | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_586' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_586', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=494562 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928a261c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.184059811 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,12,4,43,4} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,12,4,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_227] | 1 | False | 0.23 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_227' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_227', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-10' pid=494601 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde35f240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_227/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_73] | 1 | False | 0.17 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_73' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_73', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-10' pid=494685 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e874d8b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.203576091 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,64,4,64} Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,64,4,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_316] | 1 | False | 0.27 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_316' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_316', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-12' pid=494710 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080d8850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_316/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_964] | 1 | False | 0.46 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_964' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_964', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=494846 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2735c3c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.386075845 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,6,1,2,23} Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,6,1,2,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_870] | 1 | False | 0.13 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_870' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_870', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=494845 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fca490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.214123585 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_600] | 1 | False | 0.27 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_600' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_600', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=495194 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc9db3a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.300844697 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,43,12,4,4} Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,43,12,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1056] | 1 | True | 0.24 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1056' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1056', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=495106 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfd24f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21696733 bytes MEM: Free's : 26 free's of 21696733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (240, 8, 9, 13) got (2, 8, 9, 13) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_38] | 1 | False | 0.28 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_38' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_38', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=495195 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d46460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.315937697 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,32,32} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,32,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_483] | 1 | False | 0.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_483' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_483', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=495413 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a99db90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.351587561 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,2,11,9} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,2,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_333] | 1 | False | 0.26 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_333' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_333', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-12' pid=495464 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68c9690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_333/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_888] | 1 | False | 0.41 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_888' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_888', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=495610 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f255640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.531215337 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,1,16} Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,1,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_220] | 1 | False | 0.21 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_220' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_220', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-12' pid=495585 parent=477731 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fc8dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_220/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_775] | 1 | False | 0.28 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_775' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_775', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=495586 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8840720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.408041352 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,1,11} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_44] | 1 | False | 0.17 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_44' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_44', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=495692 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4172540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.387122838 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,32,1} Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,32,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_634] | 1 | False | 0.27 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_634' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_634', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-12' pid=496270 parent=478585 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e583c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_634/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1034] | 1 | True | 0.28 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1034' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1034', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=496269 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aaa88a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18865901 bytes MEM: Free's : 26 free's of 18865901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (264, 14, 4) got (4, 14, 4) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_571] | 1 | False | 0.28 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_571' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_571', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=496354 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351adbc440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.35165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.35204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.35231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.35244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.35256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.35268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.35286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.35297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.35308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.35322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.35335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.35336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.35339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.665449634 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,43,4,12} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,43,4,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_196] | 1 | False | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_196' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_196', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-14' pid=496508 parent=477748 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfb0ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_196/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_364] | 1 | False | 0.32 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_364' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_364', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=496505 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d55290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.32250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.32291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.32311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.32343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.32373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.32402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.32426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.32445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.32470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.32491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.32514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.32540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.32561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.32584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.32618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.32643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.32667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.32691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.32714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.32737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.32765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.32791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.32814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.32840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.32859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.32880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.32903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.32922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.32959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.32983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.33011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.33030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.33056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.33078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.33096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.33120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.33145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.33166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.33192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.33222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.33253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.33255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.33258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.695067249 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,99,22} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,99,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_554] | 1 | False | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_554' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_554', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=496779 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740f28aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.657446335 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,30,4,4} Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,30,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_90] | 1 | False | 0.30 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_90' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_90', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=496684 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ee0fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.26794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.26856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.26889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.26917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.26942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.26968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.26998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.706875888 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,6400} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,6400} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1038] | 1 | True | 0.37 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1038' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1038', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=497155 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe78ac40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18871501 bytes MEM: Free's : 26 free's of 18871501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (44, 6, 14, 4) got (4, 6, 14, 4) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_182] | 1 | False | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_182' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_182', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=497416 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2735d840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_182/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1050] | 1 | True | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1050' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1050', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-15' pid=497373 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92875e210 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21689713 bytes MEM: Free's : 26 free's of 21689713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (960, 2, 9, 13) got (2, 2, 9, 13) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_498] | 1 | False | 0.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_498' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_498', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=497415 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f43a290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25136s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.924417025 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{172,360,4} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{172,360,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1000] | 1 | False | 0.28 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1000' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1000', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=497418 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593932f210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.825048540 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,1,5,2,6} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,1,5,2,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_126] | 1 | False | 0.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_126' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_126', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-15' pid=497617 parent=477748 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfb0110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.821879122 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,1024} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_963] | 1 | False | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_963' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_963', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=497660 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8844490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.837175174 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,6,23,1,2} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,6,23,1,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1024] | 1 | False | 0.34 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1024' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1024', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-15' pid=497858 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa93ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.938864143 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,5,2,6} Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,5,2,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1055] | 1 | False | 0.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1055' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1055', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=497913 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740c5f910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.934364722 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,108,10,13} Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,108,10,13} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_465] | 1 | False | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_465' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_465', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=497915 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67e5940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.946403638 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,2,11,9} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,2,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1009] | 1 | False | 0.17 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1009' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1009', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-11' pid=498157 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc801600 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.912303795 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,6,2,23,5} Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,6,2,23,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_813] | 1 | False | 0.48 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_813' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_813', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=498584 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36d1860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23140s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.137042419 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,11,1,1} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,11,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_591] | 1 | False | 0.20 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_591' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_591', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=498245 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a1b4470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:12.933454192 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,4,12,43} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,4,12,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_991] | 1 | False | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_991' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_991', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=498673 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92884e6f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.015055039 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,5,2,1,6} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,5,2,1,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1006] | 1 | False | 0.21 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1006' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1006', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=498716 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52019870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.075047172 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,23,6,5} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,23,6,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_990] | 1 | False | 0.19 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_990' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_990', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-15' pid=498828 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe774100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1802s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.059059511 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,5,2,6,1} Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,5,2,6,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_557] | 1 | False | 0.28 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_557' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_557', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=498958 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376c198f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.132418997 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,30,12,43} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,30,12,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_858] | 1 | False | 0.27 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_858' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_858', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=499115 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e61340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.198415015 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,1,11,16} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,1,11,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_757] | 1 | False | 0.18 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_757' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_757', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-14' pid=499003 parent=478221 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f258d20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_757/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_230] | 1 | False | 0.17 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_230' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_230', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-14' pid=499091 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712311200 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_230/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_913] | 1 | False | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_913' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_913', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=499244 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d4fe20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.37921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.37957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.37983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.38003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.38032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.38054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.38077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.38097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.38118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.38142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.38164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.38182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.38205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.38231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.38249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.38273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.38295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.38316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.38337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.38359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.38381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.38408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.38427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.38446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.38468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.38489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.38511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.38530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.38551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.38570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.38597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.38617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.38636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.38657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.38675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.38693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.38719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.38741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.38763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.38786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.38814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.38815s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.38818s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.207556129 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,6,1,23} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,6,1,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_193] | 1 | False | 0.22 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_193' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_193', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-15' pid=499334 parent=477731 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fd5340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_193/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_642] | 1 | False | 0.19 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_642' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_642', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-13' pid=499489 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde366550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_642/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_694] | 1 | False | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_694' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_694', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-15' pid=499705 parent=478151 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179db0d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_694/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_152] | 1 | False | 0.23 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_152' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_152', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-14' pid=499788 parent=478383 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe16730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.252376255 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,2,128,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_11] | 1 | False | 0.28 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_11' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_11', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-15' pid=499842 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52018cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656263 bytes MEM: Free's : 26 free's of 18656263 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.369009434 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{3,54} Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{3,54} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_860] | 1 | False | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_860' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_860', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=499839 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa97640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.269642685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_23] | 1 | False | 0.28 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_23' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_23', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=499838 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928851920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.274256984 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,32} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_207] | 1 | False | 0.22 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_207' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_207', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-15' pid=500122 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8848cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_207/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_127] | 1 | False | 0.22 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_127' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_127', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-15' pid=500189 parent=477818 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712313880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.362708813 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,128,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_20] | 1 | False | 0.24 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_20' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_20', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=500276 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c4589b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671725 bytes MEM: Free's : 26 free's of 18671725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.356284737 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,4} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_239] | 1 | False | 0.24 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_239' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_239', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-16' pid=500645 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68d69a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_239/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_603] | 1 | False | 0.30 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_603' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_603', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-18' pid=500746 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59395171b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.460747602 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,4,30} Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_358] | 1 | False | 0.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_358' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_358', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-15' pid=500712 parent=478585 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e61d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_358/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_730] | 1 | False | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_730' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_730', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-14' pid=500710 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde369a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_730/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_687] | 1 | False | 0.16 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_687' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_687', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-16' pid=500803 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080dfdc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_687/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_981] | 1 | False | 0.33 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_981' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_981', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-15' pid=500934 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36d4b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.596495633 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,2,5,1,6} Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,2,5,1,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_781] | 1 | False | 0.28 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_781' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_781', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-15' pid=501047 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27367c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.26215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.27021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.27039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.27106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.27124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.27144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.27159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.27173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.27187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.27205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.27223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.27237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27719s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.562170732 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,16,11} Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_424] | 1 | False | 0.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_424' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_424', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=501022 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb178f2520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.520333290 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,11,9,22} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,11,9,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_572] | 1 | False | 0.30 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_572' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_572', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=501510 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe95bf70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19815s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19817s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.719550837 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,43,12,4} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,43,12,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_397] | 1 | False | 0.22 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_397' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_397', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-18' pid=501337 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9287682f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.601569874 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,22,11,11,9} Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,22,11,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_231] | 1 | False | 0.25 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_231' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_231', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-16' pid=501423 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5201cb60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_231/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_925] | 1 | False | 0.28 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_925' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_925', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-18' pid=501520 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e4c730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9704s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.697172515 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,6,23,5} Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,6,23,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1044] | 1 | False | 0.42 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1044' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1044', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=501618 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712334800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.776530952 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,1,4,11,6,14} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,1,4,11,6,14} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_561] | 1 | False | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_561' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_561', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=501812 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6abb6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.735361551 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,4,30,43} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,4,30,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_162] | 1 | False | 0.28 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_162' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_162', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=501967 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080e21d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_162/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_245] | 1 | False | 0.26 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_245' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_245', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-19' pid=502097 parent=477728 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59393379b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_245/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_241] | 1 | False | 0.36 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_241' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_241', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-18' pid=502121 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abe33d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_241/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_794] | 1 | False | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_794' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_794', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-14' pid=502358 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc80b390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.837223656 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,1,11,16} Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,1,11,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_57] | 1 | False | 0.40 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_57' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_57', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=502357 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35eb590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.27067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.27095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.27118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.27139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.27185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.27206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.27231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.27256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.27279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.27301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.27328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.28012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.28037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.28059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.28086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.28088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.28090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.043306208 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,128} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,128} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_103] | 1 | False | 0.37 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_103' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_103', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=502448 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92876b690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6975s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.893094391 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{3,80,4,80} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{3,80,4,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_693] | 1 | False | 0.24 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_693' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_693', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-16' pid=502656 parent=477887 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27366bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_693/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_500] | 1 | False | 0.28 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_500' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_500', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=502619 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52202fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:13.899386747 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1440,4,43} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1440,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_235] | 1 | False | 0.42 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_235' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_235', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-17' pid=502821 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d56ce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_235/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_731] | 1 | False | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_731' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_731', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-19' pid=502733 parent=477748 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfbe350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_731/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_65] | 1 | False | 0.20 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_65' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_65', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=503367 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d7b200 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.043443697 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,2,64,64} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,2,64,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_825] | 1 | False | 0.19 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_825' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_825', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=503242 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe21660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.025139947 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,16,11} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_130] | 1 | False | 0.29 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_130' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_130', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-20' pid=503511 parent=477728 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593933adc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.101416874 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1024,2,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_254] | 1 | False | 0.22 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_254' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_254', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-17' pid=503689 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871231a560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_254/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_89] | 1 | False | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_89' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_89', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=503757 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2727ddf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.159975496 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{76800} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{76800} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_696] | 1 | False | 0.16 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_696' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_696', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-18' pid=503849 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52023e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_696/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_616] | 1 | False | 0.43 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_616' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_616', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=503850 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe962d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.335451962 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,4,30,12} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,4,30,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_810] | 1 | False | 0.19 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_810' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_810', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-16' pid=503898 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3711f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.181943104 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,11,1} Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_340] | 1 | False | 0.31 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_340' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_340', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-19' pid=504116 parent=477744 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c45da20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_340/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_814] | 1 | False | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_814' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_814', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-18' pid=504182 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe24db0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.259693982 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,11,1,1} Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,11,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_729] | 1 | False | 0.19 | |
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[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_729' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_729', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-17' pid=504183 parent=477985 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36db180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_729/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_706] | 1 | False | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_706' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_706', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-19' pid=504423 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080e76b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_706/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_411] | 1 | False | 0.17 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_411' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_411', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=504774 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde288660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.422431844 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,2,22,11} Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,2,22,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_615] | 1 | False | 0.26 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_615' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_615', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-18' pid=504775 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740f3a9a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.422350228 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,4,12,30} Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,4,12,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1058] | 1 | False | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1058' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1058', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=504776 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f3a9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.443332212 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{864,2,130} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{864,2,130} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_837] | 1 | False | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_837' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_837', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=504854 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4181c90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.445197758 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,1,16} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,1,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_88] | 1 | False | 0.27 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_88' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_88', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=504852 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351aafd670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.2119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.493078253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,64,2,4} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,64,2,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_777] | 1 | False | 0.39 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_777' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_777', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=505016 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593933fe60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10153s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.602098909 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,1,11} Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1048] | 1 | False | 0.16 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1048' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1048', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=505173 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ef5ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.485343552 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,864,10,13} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,864,10,13} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1030] | 1 | False | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1030' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1030', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=505557 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe415f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2820s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.577292869 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,66,14} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,66,14} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_462] | 1 | False | 0.17 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_462' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_462', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=505747 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb178fa500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.544160354 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,22,2,9} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,22,2,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_472] | 1 | False | 0.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_472' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_472', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=505880 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d696c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1838s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.602554355 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,11,9,11} Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,11,9,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_563] | 1 | False | 0.27 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_563' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_563', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=506010 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c644270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.649424899 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,30,4,43} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,30,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_852] | 1 | False | 0.23 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_852' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_852', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=506011 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fe7c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.646136475 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,11,1} Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_905] | 1 | False | 0.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_905' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_905', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=506053 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4184d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.699145621 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,23,2} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,23,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_617] | 1 | False | 0.36 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_617' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_617', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=506095 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe9650c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.768403829 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,4,30} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_978] | 1 | False | 0.46 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_978' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_978', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=506172 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5202bd90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.912090255 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,2,6,5,1} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,2,6,5,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_278] | 1 | False | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_278' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_278', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-21' pid=506279 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abec3d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_278/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_98] | 1 | False | 0.31 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_98' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_98', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-18' pid=506498 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc728bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.783952148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6400,3,4} Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6400,3,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_198] | 1 | False | 0.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_198' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_198', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-19' pid=506859 parent=477985 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36ddb30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_198/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_484] | 1 | False | 0.26 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_484' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_484', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=506947 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d82ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.837594742 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,9,2,11} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,9,2,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_292] | 1 | False | 0.29 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_292' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_292', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-19' pid=507101 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde377790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_292/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_553] | 1 | False | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_553' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_553', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=507100 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523ac86c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20103s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.964330547 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,30,4,4} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,43,30,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_713] | 1 | False | 0.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_713' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_713', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-22' pid=507144 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abee660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_713/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_473] | 1 | False | 0.32 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_473' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_473', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=507279 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59efd510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.930073979 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,11,11,9} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,11,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_314] | 1 | False | 0.17 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_314' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_314', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-21' pid=507304 parent=478387 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4185cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_314/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_864] | 1 | False | 0.30 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_864' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_864', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=507671 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080f3000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.048450666 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,1,16} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,1,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_618] | 1 | False | 0.27 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_618' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_618', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=507666 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8a38c90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:14.967968571 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,30,4} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,30,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_387] | 1 | False | 0.34 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_387' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_387', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=507655 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67f8660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1921s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.072748441 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,9,22,11} Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,9,22,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_894] | 1 | False | 0.29 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_894' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_894', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=507974 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273711d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.141156635 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{60,23,1} Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{60,23,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_346] | 1 | False | 0.20 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_346' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_346', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-21' pid=507975 parent=477740 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe784eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_346/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_973] | 1 | False | 0.27 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_973' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_973', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=508043 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abf1c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9811s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9814s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.150719098 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,1,2,23,6} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,1,2,23,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_32] | 1 | False | 0.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_32' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_32', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=508304 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939346470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.171608919 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,32,32} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,32,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_763] | 1 | False | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_763' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_763', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=508158 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a418c040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.150368041 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,11} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_115] | 1 | False | 0.24 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_115' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_115', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=508358 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d85d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.163854106 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,80,3,4} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,80,3,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_791] | 1 | False | 0.19 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_791' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_791', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=508357 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d630e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.151164221 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,1,11} Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_679] | 1 | False | 0.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_679' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_679', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-21' pid=508359 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5202db10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_679/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_520] | 1 | False | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_520' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_520', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=508737 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523ac8a940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.231422486 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,12,43,4} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,12,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_752] | 1 | False | 0.19 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_752' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_752', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-22' pid=508738 parent=477744 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c465e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_752/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_648] | 1 | False | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_648' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_648', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-22' pid=508776 parent=477748 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfc5880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_648/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_461] | 1 | False | 0.17 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_461' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_461', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=508915 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f17d0b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.271843764 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,9,22,2} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,9,22,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_655] | 1 | False | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_655' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_655', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-23' pid=508957 parent=477737 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e572c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_655/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_719] | 1 | False | 0.20 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_719' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_719', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-20' pid=509002 parent=477988 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc8188a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_719/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_515] | 1 | False | 0.23 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_515' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_515', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=509249 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe96b870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.345354906 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,30,12,43} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,30,12,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_282] | 1 | False | 0.19 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_282' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_282', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-22' pid=509207 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68e59b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_282/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_453] | 1 | False | 0.20 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_453' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_453', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=509291 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f46600 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.334587732 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,22,11} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,22,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_159] | 1 | False | 0.16 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_159' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_159', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=509295 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179eaf60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_159/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_199] | 1 | False | 0.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_199' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_199', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-22' pid=509293 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d63af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_199/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_807] | 1 | False | 0.27 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_807' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_807', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=509518 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36e6210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.431005492 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,1,11} Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_873] | 1 | False | 0.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_873' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_873', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=509563 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abf7450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.432065504 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,11,16,1} Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,11,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_547] | 1 | False | 0.37 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_547' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_547', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=509564 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03e00117f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23403s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.531347466 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,30,43,4,4} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,30,43,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_451] | 1 | False | 0.23 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_451' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_451', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=510041 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c37e470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5981s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.520907789 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,22,11,9} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,22,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_707] | 1 | False | 0.17 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_707' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_707', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-21' pid=510017 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde37d310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_707/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_605] | 1 | False | 0.41 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_605' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_605', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=510086 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376c1a94f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2156s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.636700145 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,4,12,30} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,4,12,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_596] | 1 | False | 0.31 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_596' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_596', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=510084 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d2803d5e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.557361912 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,43,12,4} Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,43,12,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_505] | 1 | False | 0.21 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_505' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_505', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=510110 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17bd2c90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.532365893 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5160,48} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5160,48} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1057] | 1 | False | 0.27 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1057' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1057', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=510349 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712237780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.624029384 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{18,96,10,13} Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{18,96,10,13} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_256] | 1 | False | 0.43 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_256' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_256', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-23' pid=510442 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d68430 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_256/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_933] | 1 | False | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_933' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_933', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=510443 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52034840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1736s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.575480182 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,2,23,1,5} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,2,23,1,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_446] | 1 | False | 0.20 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_446' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_446', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=510956 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35fdb50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1704s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.692204865 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,9,11,22} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,9,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_893] | 1 | False | 0.19 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_893' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_893', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=511040 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aaaf460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.726083247 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1380} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1380} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_216] | 1 | False | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_216' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_216', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-21' pid=511067 parent=477887 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273755d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_216/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_570] | 1 | False | 0.19 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_570' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_570', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=511043 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f4504a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1346s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.697396798 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,12,43,4} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,12,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_955] | 1 | False | 0.17 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_955' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_955', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=511365 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179f4310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15753s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.756163315 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,6,1,23} Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,6,1,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_356] | 1 | False | 0.22 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_356' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_356', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-23' pid=511521 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e885dd00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_356/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1053] | 1 | True | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1053' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1053', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=511522 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67ff6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1791s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21697773 bytes MEM: Free's : 26 free's of 21697773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (216, 80, 13) got (2, 80, 13) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_478] | 1 | False | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_478' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_478', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=511678 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d74360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.862609163 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,11,2,11} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,11,2,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_854] | 1 | False | 0.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_854' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_854', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=512158 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3832c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1615s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.924139056 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,11,1} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_876] | 1 | False | 0.16 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_876' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_876', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=512160 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179f8f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13249s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13251s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.940931688 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,11,1} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_428] | 1 | False | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_428' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_428', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-22' pid=512610 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2728c000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:15.984751555 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,11,22} Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,2,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_371] | 1 | False | 0.23 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_371' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_371', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-23' pid=512736 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7341a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10527s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.035130885 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2178,2,11} Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2178,2,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_31] | 1 | False | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_31' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_31', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=512805 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c4702f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.031240435 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,32,32} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,32,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_299] | 1 | False | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_299' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_299', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-24' pid=512804 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d66d00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_299/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_541] | 1 | False | 0.11 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_541' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_541', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=512871 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae2405f780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.037171383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,43,4,30} Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,43,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1059] | 1 | True | 0.19 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1059' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1059', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=512872 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfd465c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21689453 bytes MEM: Free's : 26 free's of 21689453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (1080, 16, 13) got (2, 16, 13) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_844] | 1 | False | 0.35 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_844' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_844', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=512961 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ff37c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.103945237 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,16,1} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_949] | 1 | False | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_949' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_949', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=512969 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abfcd70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.115064867 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,1,2,23,5} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,1,2,23,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1062] | 1 | False | 0.36 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1062' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1062', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=512962 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d77d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.160604301 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,13,10,9,8,2} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,13,10,9,8,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_532] | 1 | False | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_532' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_532', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=513070 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825082db730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.107428318 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,4,43,30} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,4,43,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_146] | 1 | False | 0.32 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_146' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_146', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-26' pid=513361 parent=478151 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179f9a10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.206386435 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,2,128,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_114] | 1 | False | 0.19 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_114' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_114', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=513189 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f4ca10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.104748135 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,4,80,3} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,4,80,3} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_957] | 1 | False | 0.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_957' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_957', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=513362 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f275f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6721s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6723s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.134615618 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,23,1,6} Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,23,1,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_771] | 1 | False | 0.21 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_771' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_771', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=513661 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e80530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.201735741 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{121,16} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{121,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_61] | 1 | False | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_61' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_61', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=513702 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bee05d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.218565124 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,2,64} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,2,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_671] | 1 | False | 0.20 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_671' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_671', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-24' pid=514177 parent=477985 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36ee290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_671/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_960] | 1 | False | 0.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_960' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_960', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=514244 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d6be40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17909s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.297151820 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,6,2,23,1} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,6,2,23,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_588] | 1 | False | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_588' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_588', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=514439 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4376e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.343385358 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,12,4,43,4} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,12,4,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_383] | 1 | False | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_383' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_383', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=514438 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f51850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.375112366 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,11,22,9} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,11,22,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_232] | 1 | False | 0.26 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_232' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_232', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-27' pid=514482 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080fad00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_232/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_228] | 1 | False | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_228' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_228', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-25' pid=514658 parent=478221 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f274c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_228/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_725] | 1 | False | 0.17 | |
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[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_725' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_725', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-26' pid=514828 parent=478585 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e81190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_725/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_273] | 1 | False | 0.18 | |
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[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_273' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_273', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-27' pid=514831 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928869980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_273/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1018] | 1 | False | 0.31 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1018' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1018', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=514832 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac00c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.509279939 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,5,23,2,6} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,5,23,2,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_821] | 1 | False | 0.30 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_821' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_821', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=514835 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ff5150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.570363656 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,16,11,11} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,16,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_720] | 1 | False | 0.22 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_720' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_720', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-26' pid=514886 parent=477728 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593934aa60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_720/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_320] | 1 | False | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_320' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_320', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-27' pid=514952 parent=478151 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179fd780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_320/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_611] | 1 | False | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_611' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_611', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=514885 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d28048290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.475341920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,4,4,30} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,4,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_50] | 1 | False | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_50' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_50', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=515199 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde389b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.521085685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,32,1} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,32,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_594] | 1 | False | 0.23 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_594' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_594', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=515458 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c656070 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.569369118 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,12,43,4} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,12,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_737] | 1 | False | 0.17 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_737' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_737', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-27' pid=515501 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5203f5b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_737/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1039] | 1 | True | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1039' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1039', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=515591 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e887d510 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16028s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18869261 bytes MEM: Free's : 26 free's of 18869261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (66, 4, 56) got (4, 4, 56) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_656] | 1 | False | 0.19 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_656' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_656', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-26' pid=515739 parent=478221 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f276a10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_656/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_407] | 1 | False | 0.36 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_407' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_407', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=515828 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27294170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.819146403 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,11,22,2} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,11,22,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_714] | 1 | False | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_714' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_714', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-28' pid=515969 parent=477737 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e67b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_714/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_188] | 1 | False | 0.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_188' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_188', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=516132 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7933c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_188/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_108] | 1 | False | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_108' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_108', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=516160 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bee6e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.702944048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,80,80,3} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,80,80,3} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_129] | 1 | False | 0.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_129' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_129', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-28' pid=516216 parent=478151 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179fd640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1698s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.736701805 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{256,8,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_215] | 1 | False | 0.35 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_215' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_215', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-26' pid=516407 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde38a460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_215/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_361] | 1 | False | 0.34 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_361' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_361', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=516486 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59392625e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.872425463 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{47916} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{47916} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_884] | 1 | False | 0.26 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_884' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_884', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=516485 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36f3e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.785361345 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_530] | 1 | False | 0.22 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_530' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_530', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=516487 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a437bd60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.806360563 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,30,4,12} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,30,4,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_732] | 1 | False | 0.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_732' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_732', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-27' pid=516488 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d6e940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_732/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_36] | 1 | False | 0.25 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_36' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_36', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=516619 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508103e10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.846689034 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,32,1} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,32,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_783] | 1 | False | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_783' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_783', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=516668 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac04620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.847877287 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,16,11} Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_97] | 1 | False | 0.22 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_97' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_97', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=516743 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8779e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.848849878 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{320,3,80} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{320,3,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_184] | 1 | False | 0.19 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_184' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_184', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=517210 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92886b530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_184/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_769] | 1 | False | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_769' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_769', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=517299 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfd95e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.961356246 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{176,1,11} Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{176,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_818] | 1 | False | 0.34 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_818' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_818', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=517447 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e899a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:16.994192064 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,11,1} Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_519] | 1 | False | 0.29 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_519' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_519', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=517448 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523ac9ae80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.046125323 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,12,4,43} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,30,12,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_548] | 1 | False | 0.31 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_548' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_548', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=517649 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17be50c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22785s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.119351578 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,30,43,4,4} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,30,43,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_533] | 1 | False | 0.24 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_533' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_533', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=517577 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ade8950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.016338048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,4,43} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_66] | 1 | False | 0.40 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_66' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_66', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=517585 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40b1f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19073s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.211105042 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,2,64,64} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,2,64,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_224] | 1 | False | 0.20 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_224' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_224', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-27' pid=517648 parent=477985 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36f3cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_224/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_877] | 1 | False | 0.22 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_877' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_877', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=518275 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52045620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1578s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.195657000 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,1,11} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_896] | 1 | False | 0.25 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_896' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_896', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=518487 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe799300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.220054034 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{46,30,1} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{46,30,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_787] | 1 | False | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_787' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_787', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=518602 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f280e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1646s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.228106566 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,1,16,11} Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,1,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1012] | 1 | False | 0.25 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1012' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1012', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=518754 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36f8620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4038s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.303095029 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,6,23,2,5} Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,6,23,2,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_778] | 1 | False | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_778' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_778', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=518904 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d76dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1686s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.308197148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,11,1} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_560] | 1 | False | 0.24 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_560' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_560', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=518905 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b275684f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.376563020 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,43,30,12} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,43,30,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_307] | 1 | False | 0.15 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_307' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_307', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-29' pid=519045 parent=477744 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c478fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_307/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_68] | 1 | False | 0.39 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_68' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_68', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=519301 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712244e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.489623440 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,64,64,2} Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,64,64,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_901] | 1 | False | 0.31 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_901' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_901', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=519300 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe3cce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.403478454 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{10,6,23} Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{10,6,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1026] | 1 | True | 0.19 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1026' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1026', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=519428 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e690f320 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6990s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18864801 bytes MEM: Free's : 26 free's of 18864801 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (14784,) got (4,) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_55] | 1 | False | 0.18 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_55' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_55', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=519520 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc73e960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.408483309 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32768} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32768} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_846] | 1 | False | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_846' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_846', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=519835 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41a4720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.498248503 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_154] | 1 | False | 0.40 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_154' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_154', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-29' pid=519986 parent=478221 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f282860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.39334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.39366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.39392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.39413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.39445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.39467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.39491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.39514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.39538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.39560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.39584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.39604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.39629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.39654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.39677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.39700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.39723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.39745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.39764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.39794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.39819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.39845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.39871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.39890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.39914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.39943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.39963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.39986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.40012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.40033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.40056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.40083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.40108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.40128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.40153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.40172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.40194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.40217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.40239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.40260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.40293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.40297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.40299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.667539512 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,8,128,2} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_122] | 1 | False | 0.29 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_122' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_122', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=520015 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c390a10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17052s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.574312602 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,80,4,3} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,80,4,3} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_898] | 1 | False | 0.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_898' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_898', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=520232 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e8eed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.608305851 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{10,6,23} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{10,6,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_723] | 1 | False | 0.26 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_723' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_723', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-30' pid=520415 parent=477728 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939352400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_723/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_910] | 1 | False | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_910' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_910', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=521029 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f6e8f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.2268s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.2270s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.2357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3838s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.715319496 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,6,1,5,23} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,6,1,5,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_45] | 1 | False | 0.21 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_45' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_45', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=521071 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe42e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1705s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1707s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.690273792 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,1,2,32} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,1,2,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_832] | 1 | False | 0.24 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_832' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_832', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-32' pid=521097 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aac0670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.730137141 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,11,1} Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_812] | 1 | False | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_812' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_812', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=521096 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8871940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1787s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.777133745 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,11,1} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_604] | 1 | False | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_604' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_604', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=521145 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376c1bfa10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.753392775 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,30,4} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,4,12,30,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_927] | 1 | False | 0.17 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_927' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_927', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=521146 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712335a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.748131871 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,5,23,6} Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1,5,23,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_370] | 1 | False | 0.21 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_370' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_370', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=521277 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1791ca80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5851s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.768552134 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{198,11,22} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{198,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_786] | 1 | False | 0.26 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_786' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_786', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-32' pid=521278 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41a6aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.841524020 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,11,1} Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_344] | 1 | False | 0.45 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_344' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_344', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-32' pid=521691 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928872ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_344/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_4] | 1 | False | 0.19 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_4' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_4', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=521540 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36fbf00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656599 bytes MEM: Free's : 26 free's of 18656599 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.814463947 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{174,1} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{174,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_940] | 1 | False | 0.35 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_940' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_940', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=521714 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c480480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1679s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.882246880 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,1,2,23} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,1,2,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1047] | 1 | True | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1047' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1047', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=521625 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2a5f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3583s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21827773 bytes MEM: Free's : 26 free's of 21827773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (16, 1080, 13) got (2, 1080, 13) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_885] | 1 | False | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_885' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_885', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-29' pid=521768 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc833c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.924099531 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,11,1,16} Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,11,1,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_270] | 1 | False | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_270' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_270', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-33' pid=521840 parent=477737 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e72a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_270/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_653] | 1 | False | 0.26 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_653' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_653', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-31' pid=521991 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d774e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_653/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_336] | 1 | False | 0.29 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_336' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_336', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-31' pid=522056 parent=478585 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e8da60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_336/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_480] | 1 | False | 0.24 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_480' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_480', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-27' pid=522169 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871224b6d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.935639212 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,11,2,11} Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,11,2,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1032] | 1 | False | 0.29 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1032' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1032', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=522170 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe60880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:17.946297805 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{176,1,6,14} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{176,1,6,14} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_573] | 1 | False | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_573' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_573', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=522171 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f466a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.035796234 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,4,12,30} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,4,12,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_684] | 1 | False | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_684' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_684', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-31' pid=522391 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f6e8c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_684/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1035] | 1 | False | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1035' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1035', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=522392 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250812a820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909997 bytes MEM: Free's : 26 free's of 18909997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.006618304 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{264,4,14} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{264,4,14} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_677] | 1 | False | 0.22 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_677' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_677', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-32' pid=522395 parent=477731 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ffdf60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_677/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_384] | 1 | False | 0.23 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_384' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_384', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=522642 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2a7640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1906s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.109777681 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,22,9,11} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,22,9,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_139] | 1 | False | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_139' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_139', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-34' pid=522576 parent=477737 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e74250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1778s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1781s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.086385850 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{8,2,128,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_274] | 1 | False | 0.24 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_274' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_274', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-32' pid=523262 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac0c580 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_274/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_137] | 1 | False | 0.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_137' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_137', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-32' pid=523329 parent=478585 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e8fd00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.240400998 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,128,8,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1008] | 1 | False | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1008' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1008', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=523489 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aac5d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1588s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.299195870 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,6,2,5,23} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,6,2,5,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_34] | 1 | False | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_34' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_34', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=523538 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8877420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1749s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.269065523 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,32,1} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,32,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_138] | 1 | False | 0.42 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_138' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_138', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-35' pid=523613 parent=477783 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250810e8f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.447001863 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,128,128,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_859] | 1 | False | 0.17 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_859' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_859', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=523534 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe48e10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2496s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.275056524 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,1,11} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_325] | 1 | False | 0.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_325' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_325', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-31' pid=523912 parent=477734 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3959e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_325/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_733] | 1 | False | 0.22 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_733' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_733', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-33' pid=524144 parent=478652 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928872c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_733/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_391] | 1 | False | 0.41 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_391' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_391', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-32' pid=524405 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f19f040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.26776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.26836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.26873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.26899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.26921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.26944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.26964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.26987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.569777785 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,22,11,9} Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,22,11,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_415] | 1 | False | 0.35 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_415' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_415', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-33' pid=524493 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179232a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.528755691 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,22,11,2} Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,22,11,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_33] | 1 | False | 0.32 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_33' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_33', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-32' pid=524641 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe4cbe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2058s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.574912721 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,1,32} Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,1,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_811] | 1 | False | 0.30 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_811' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_811', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-33' pid=524643 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f78cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.545178310 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,1,11} Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,1,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_750] | 1 | False | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_750' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_750', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-32' pid=524644 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8874350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_750/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_612] | 1 | False | 0.29 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_612' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_612', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-33' pid=524714 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939462ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.572567799 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,4,30,4} Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,4,30,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_409] | 1 | False | 0.25 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_409' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_409', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=524715 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bef8bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.493576869 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,22,11,2} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,22,11,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_48] | 1 | False | 0.41 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_48' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_48', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-35' pid=525298 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aacb0f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.753082882 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,32,1,2} Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,32,1,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_388] | 1 | False | 0.41 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_388' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_388', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-35' pid=525382 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40bfcd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.777591113 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,11,9,22} Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,11,9,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_614] | 1 | False | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_614' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_614', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=525447 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bca17e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.723010322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,30,4,4} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,30,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_96] | 1 | False | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_96' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_96', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-31' pid=525256 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272a4890 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.595210874 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{320,3,80} Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{320,3,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_998] | 1 | False | 0.26 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_998' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_998', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=525300 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a006e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18854s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18857s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.707284713 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,1,6,2,5} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,1,6,2,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_249] | 1 | False | 0.25 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_249' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_249', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-36' pid=525773 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508112c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_249/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_102] | 1 | False | 0.14 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_102' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_102', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=526037 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51e8d7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1958s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.794341428 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{3,80,80,4} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{3,80,80,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_83] | 1 | False | 0.23 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_83' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_83', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=526208 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6815220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.836459659 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,4,2,64} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,4,2,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_236] | 1 | False | 0.22 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_236' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_236', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-33' pid=526232 parent=478383 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe4c500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_236/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_982] | 1 | False | 0.34 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_982' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_982', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=526387 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17a12460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.026527871 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,2,1,6,5} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,2,1,6,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_795] | 1 | False | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_795' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_795', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=526307 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939287140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1508s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.831461323 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,16,1} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_54] | 1 | False | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_54' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_54', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=526452 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e7c980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.902171386 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,32,1,2} Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,32,1,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_621] | 1 | False | 0.28 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_621' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_621', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-33' pid=526561 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f470840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.969556592 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,30,4,12,4} Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,30,4,12,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_167] | 1 | False | 0.11 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_167' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_167', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-35' pid=526559 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a007150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_167/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_865] | 1 | False | 0.29 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_865' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_865', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=526585 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e98880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.990067098 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,16,1,1} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,16,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_94] | 1 | False | 0.29 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_94' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_94', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-30' pid=526691 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122527a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:18.999144181 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{240,4,80} Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{240,4,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_303] | 1 | False | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_303' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_303', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-37' pid=526828 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508114680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_303/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_252] | 1 | False | 0.29 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_252' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_252', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-35' pid=526833 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f7bcd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_252/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_539] | 1 | False | 0.40 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_539' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_539', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=527193 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523acacd90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.132s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.122346794 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,4,43} Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_133] | 1 | False | 0.27 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_133' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_133', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-34' pid=527105 parent=477985 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3702fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.049527942 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,8,128,128} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_736] | 1 | False | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_736' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_736', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-36' pid=527259 parent=477748 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfe7cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_736/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_200] | 1 | False | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_200' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_200', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-36' pid=527373 parent=478387 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41adc50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_200/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_537] | 1 | False | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_537' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_537', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=527506 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740e874f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.141383916 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,4,30,43} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,4,30,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_64] | 1 | False | 0.15 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_64' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_64', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-33' pid=527618 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272a8ea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.142229959 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4096,4,2} Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4096,4,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1020] | 1 | False | 0.42 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1020' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1020', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=527703 parent=477740 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7a4ad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1596s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.372473947 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,2,6,5} Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,23,2,6,5} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_471] | 1 | False | 0.29 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_471' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_471', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=527896 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250802bee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.275156204 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,9,11,11} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,2,9,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_155] | 1 | False | 0.30 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_155' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_155', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-31' pid=528009 parent=477818 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871233ea70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.303435665 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,128,2,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_189] | 1 | False | 0.09 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_189' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_189', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=528125 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27da0f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_189/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_240] | 1 | False | 0.44 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_240' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_240', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-35' pid=528183 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e887b1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_240/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_331] | 1 | False | 0.33 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_331' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_331', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-34' pid=528424 parent=477887 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27397cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_331/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_802] | 1 | False | 0.19 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_802' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_802', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-35' pid=528601 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3a1bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.393255156 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,11,1} Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_179] | 1 | False | 0.16 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_179' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_179', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=528632 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aacbf60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_179/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_583] | 1 | False | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_583' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_583', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=528864 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928a609b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.519560153 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,43,12,4} Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{30,4,43,12,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_260] | 1 | False | 0.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_260' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_260', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-38' pid=529276 parent=477748 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfecf10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_260/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1054] | 1 | False | 0.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1054' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1054', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=529407 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1784faa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.628338229 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11232,2,10} Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11232,2,10} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_486] | 1 | False | 0.20 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_486' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_486', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=529490 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f227e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4892s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4894s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.567140036 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,11,2,9} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,11,2,9} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_218] | 1 | False | 0.17 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_218' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_218', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-38' pid=529584 parent=477852 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aaced90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_218/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_2] | 1 | False | 0.26 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_2' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_2', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=530019 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6908330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.30240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.30298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.30319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.30348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.30377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.30400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.30421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.30446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.30466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.30497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.30518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.30538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.30564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.30599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.30620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.30641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.30668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.30688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.30713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.30740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.30765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.30792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.30816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.30834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.30856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.30881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.30903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.30922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.30944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.30964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.30991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.31012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.31032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.31050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.31075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.31094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.31123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.31152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.31173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.31198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.31232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.31236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.31239s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656599 bytes MEM: Free's : 26 free's of 18656599 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.783122882 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,87} Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,87} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_105] | 1 | False | 0.23 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_105' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_105', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=530084 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740bbee50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.779155418 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,3,80,80} Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,3,80,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_789] | 1 | False | 0.41 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_789' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_789', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-35' pid=530127 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2739d330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.901972391 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,16,1} Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_323] | 1 | False | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_323' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_323', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-36' pid=530126 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e887e6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_323/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_330] | 1 | False | 0.23 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_330' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_330', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-34' pid=530223 parent=477988 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc83b1f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_330/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_535] | 1 | False | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_535' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_535', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=530646 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523acb4fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:19.870427326 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,43,4,30} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,43,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_297] | 1 | False | 0.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_297' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_297', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-37' pid=531181 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740cada70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_297/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_402] | 1 | False | 0.31 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_402' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_402', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=531447 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8796940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.069668597 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,2,22,11,11} Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,2,22,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_722] | 1 | False | 0.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_722' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_722', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-35' pid=531373 parent=477988 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc83d660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_722/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_749] | 1 | False | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_749' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_749', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-36' pid=531396 parent=477740 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7a6180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_749/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_939] | 1 | False | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_939' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_939', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=531709 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3a8e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15037s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15039s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.167599511 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,23,1,2} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,23,1,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_280] | 1 | False | 0.32 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_280' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_280', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-37' pid=531752 parent=478383 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe55240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_280/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_751] | 1 | False | 0.22 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_751' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_751', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-34' pid=531796 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712347ed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_751/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1027] | 1 | True | 0.22 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1027' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1027', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=531797 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51fa1d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18877101 bytes MEM: Free's : 26 free's of 18877101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (24, 11, 14, 4) got (4, 11, 14, 4) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_966] | 1 | False | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_966' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_966', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=532100 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508121470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.163s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.256093555 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,23,2,6,1} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,23,2,6,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_806] | 1 | False | 0.23 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_806' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_806', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=532076 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273a0e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.207405854 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,11,1} Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,11,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_163] | 1 | False | 0.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_163' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_163', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=532273 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a0117b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_163/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_534] | 1 | False | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_534' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_534', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=532426 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27f8c450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.276247095 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,43,4} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_941] | 1 | False | 0.27 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_941' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_941', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=532491 parent=477748 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bff26a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17141s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17143s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.375213636 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,1,23,2} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{6,5,1,23,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_351] | 1 | False | 0.39 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_351' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_351', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-39' pid=532516 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e690e6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_351/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_328] | 1 | False | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_328' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_328', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-37' pid=532517 parent=477740 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7a8cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_328/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_504] | 1 | False | 0.26 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_504' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_504', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=532518 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bca240f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.312787379 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{15480,4,4} Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{15480,4,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_881] | 1 | False | 0.21 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_881' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_881', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=532801 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac1f8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.394153020 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,1,16,11} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,1,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_774] | 1 | False | 0.13 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_774' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_774', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=532802 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3ab8b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3670s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.362153396 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,1,11,11} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,1,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_986] | 1 | False | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_986' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_986', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=533192 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273a24f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.474206924 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,6,5,2,1} Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{23,6,5,2,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1004] | 1 | False | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1004' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1004', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=533193 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe58260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.502829679 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,5,6,23} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,5,6,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_906] | 1 | False | 0.28 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_906' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_906', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=533646 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a01a9c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.617276996 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,6,5,23,1} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,6,5,23,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_625] | 1 | False | 0.45 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_625' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_625', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=533908 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ae013b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.789503617 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,30,4,4,12} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,30,4,4,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_891] | 1 | False | 0.31 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_891' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_891', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=534103 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aadb2d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.724449434 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,1,16} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,1,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_132] | 1 | False | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_132' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_132', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -6 E assert -6 == 0 E + where -6 = <Process name='Process-42' pid=534104 parent=478387 stopped exitcode=-SIGABRT>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41ba240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.717582645 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16384,2,8} terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_29] | 1 | False | 0.41 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_29' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_29', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=534193 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928884010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.784362320 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,32} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{32,2,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_315] | 1 | False | 0.23 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_315' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_315', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-40' pid=534442 parent=478084 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e690e7a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_315/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1005] | 1 | False | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1005' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1005', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=534518 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59392940b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.736425786 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,5,23,6} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,2,5,23,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_430] | 1 | False | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_430' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_430', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=534736 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde1e6250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.837130322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,11,2,22} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,9,11,2,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_204] | 1 | False | 0.21 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_204' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_204', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-39' pid=534825 parent=477740 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7aba50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_204/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_396] | 1 | False | 0.33 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_396' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_396', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=534870 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c3a3180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6901s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.891310462 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,22,11,9,11} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,22,11,9,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_77] | 1 | False | 0.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_77' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_77', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=534894 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740bcc150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.888112219 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,4,2,64} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,4,2,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_650] | 1 | False | 0.14 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_650' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_650', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-40' pid=534895 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8885820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_650/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_545] | 1 | False | 0.22 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_545' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_545', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=535369 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f47f310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.943558920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,30,4,4,43} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,30,4,4,43} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_386] | 1 | False | 0.25 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_386' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_386', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=535446 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b271ded80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5262s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:20.978588170 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,9,11,22} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,9,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_25] | 1 | False | 0.38 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_25' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_25', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=535455 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc848d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.111568642 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,32} Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,32,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_923] | 1 | False | 0.36 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_923' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_923', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=535454 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f8fb30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.48461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.48512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.48540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.48566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.48597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.48619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.48640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.48665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.48689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.48716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.48743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.48764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.48783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.48816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.48835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.48858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.48881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.48901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.48924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.48960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.48981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.49004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.49031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.49050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.49068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.49094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.49121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.49146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.49173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.49192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.49219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.49243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.49267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.49303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.49327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.49346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.49371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.49395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.49414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.49439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.49477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.49481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.49483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.109655022 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,1,5,6} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,1,5,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_843] | 1 | False | 0.30 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_843' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_843', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=535581 parent=477985 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3632c70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.125480254 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,1,16} Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,11,1,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_366] | 1 | False | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_366' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_366', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=535589 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40d18a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.039137216 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,242} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,242} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_404] | 1 | False | 0.25 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_404' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_404', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=535771 parent=478151 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1785ca00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1624s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.074122495 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,2,11,22} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{9,11,2,11,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_377] | 1 | False | 0.14 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_377' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_377', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=536007 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23dbb6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.068348000 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,9,11,22,11} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,9,11,22,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_727] | 1 | False | 0.28 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_727' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_727', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-37' pid=536364 parent=477818 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871234b190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_727/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_785] | 1 | False | 0.22 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_785' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_785', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=536363 parent=478221 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f29fda0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.156414911 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,1,11} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_820] | 1 | False | 0.23 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_820' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_820', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=536366 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c494ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.162154491 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,11,1,1} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,11,11,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_529] | 1 | False | 0.19 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_529' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_529', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=536368 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740e9d8f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.226315115 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,30,12,4} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,30,12,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_776] | 1 | False | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_776' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_776', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=536414 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2d9fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.265083881 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,11,1} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_275] | 1 | False | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_275' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_275', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-39' pid=536415 parent=477887 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272cbc90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_275/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_233] | 1 | False | 0.27 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_233' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_233', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-41' pid=536656 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ab44dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_233/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_914] | 1 | False | 0.18 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_914' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_914', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=536892 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939299020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.301290667 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,23,6,1} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,23,6,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_526] | 1 | False | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_526' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_526', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-44' pid=536944 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27f980c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.317068998 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,12,30,4} Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,12,30,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1037] | 1 | True | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1037' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1037', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=536945 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080677d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18865661 bytes MEM: Free's : 26 free's of 18865661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (336, 11, 4) got (4, 11, 4) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_175] | 1 | False | 0.14 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_175' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_175', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=537306 parent=478186 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f92120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_175/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_423] | 1 | False | 0.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_423' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_423', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=537348 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740bd5ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.434865253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,9,22,11} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,9,22,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_263] | 1 | False | 0.16 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_263' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_263', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-45' pid=537349 parent=477731 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a01f660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_263/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_511] | 1 | False | 0.23 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_511' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_511', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=537351 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b274b3120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.486642420 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,43,4,30} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,12,43,4,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_958] | 1 | False | 0.23 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_958' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_958', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=537352 parent=477988 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc84bcc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.416066668 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,1,6,23} Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{5,2,1,6,23} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_311] | 1 | False | 0.18 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_311' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_311', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-44' pid=537392 parent=478387 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40e4620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_311/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_772] | 1 | False | 0.34 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_772' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_772', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=537577 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2de7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.537159318 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,121,1} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{16,1,121,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_109] | 1 | False | 0.28 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_109' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_109', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=537749 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59391ae800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.534157836 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,80,3,80} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,80,3,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_829] | 1 | False | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_829' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_829', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=537750 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23ead5e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.35544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.35584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.35605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.35635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.35655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.35681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.35709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.35733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.35753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.35776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.35796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.35816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.35837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.35858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.35879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.35901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.35925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.35943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.35963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.35985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.36007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.36030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.36055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.36078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.36098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.36121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.36141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.36164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.36184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.36212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.36239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.36261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.36283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.36311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.36313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.36316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.678075442 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,1,11} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,16,11,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1061] | 1 | False | 0.34 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1061' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1061', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=537707 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e682a1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2243s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.692384366 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,8,9,10,13,12} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,8,9,10,13,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_345] | 1 | False | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_345' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_345', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-42' pid=537775 parent=478286 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ab47610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_345/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_527] | 1 | False | 0.27 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_527' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_527', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-46' pid=537954 parent=477783 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825082325f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.660418583 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,4,12,30} Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,43,4,12,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1060] | 1 | True | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1060' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1060', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=538003 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e879fff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21968173 bytes MEM: Free's : 26 free's of 21968173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (8, 12, 9, 130, 2) got (2, 12, 9, 130, 2) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_912] | 1 | False | 0.23 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_912' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_912', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-46' pid=538070 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a022230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.608069104 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,6,23,1} Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,5,6,23,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_921] | 1 | False | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_921' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_921', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=538600 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272d6170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.674335475 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,5,1,6} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,5,1,6} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_24] | 1 | False | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_24' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_24', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=538708 parent=477852 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa07860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18696301 bytes MEM: Free's : 26 free's of 18696301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.726600983 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,32} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{64,32} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_243] | 1 | False | 0.18 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_243' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_243', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-40' pid=538641 parent=478221 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f1c46c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_243/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_460] | 1 | False | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_460' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_460', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=538665 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a3ffc970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.731811493 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,9,2,22} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,9,2,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_643] | 1 | False | 0.23 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_643' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_643', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-44' pid=538732 parent=478427 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740cc2fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_643/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_853] | 1 | False | 0.24 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_853' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_853', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=538877 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c49afe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.771172586 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,1,11} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,16,1,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_62] | 1 | False | 0.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_62' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_62', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-46' pid=538928 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27ccec80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19275885 bytes MEM: Free's : 26 free's of 19275885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.760494748 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,4,64} Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{128,4,64} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_839] | 1 | False | 0.25 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_839' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_839', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=538993 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfd83630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.818127382 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,1,16,11} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,1,16,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_390] | 1 | False | 0.29 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_390' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_390', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=539040 parent=478519 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e87a2d90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.849151048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,22,9,11} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,11,22,9,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_251] | 1 | False | 0.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_251' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_251', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-43' pid=539171 parent=477728 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593929e6c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_251/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_863] | 1 | False | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_863' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_863', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=539172 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9287aebc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2093s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.899050204 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,16,1} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,11,1,16,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_610] | 1 | False | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_610' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_610', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-44' pid=539215 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde4c2f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5044s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.900637618 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,4,30,4} Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{43,12,4,30,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_635] | 1 | False | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_635' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_635', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-45' pid=539327 parent=478186 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f948d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_635/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_113] | 1 | False | 0.27 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_113' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_113', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=539240 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b271ec3c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.11102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.972127549 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,4,3,80} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,4,3,80} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_668] | 1 | False | 0.18 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_668' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_668', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-47' pid=539370 parent=477783 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508053990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_668/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_663] | 1 | False | 0.29 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_663' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_663', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-44' pid=539407 parent=478151 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1794f090 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_663/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_120] | 1 | False | 0.25 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_120' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_120', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-44' pid=539547 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e682cbe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.971145753 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,4,80,3} Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,4,80,3} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_363] | 1 | False | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_363' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_363', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-47' pid=539768 parent=477737 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27cd30e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:21.986099342 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1089,22} Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,1089,22} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_895] | 1 | False | 0.28 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_895' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_895', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-46' pid=539851 parent=478387 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40ee020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.038168218 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,690,1} Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,690,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_476] | 1 | False | 0.23 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_476' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_476', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=540073 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c3adfa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3801s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.067054580 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,2,11,11} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,9,2,11,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_485] | 1 | False | 0.27 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_485' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_485', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=540156 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740bdbe40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4094s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.063995355 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,9,11,2} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{22,11,9,11,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_845] | 1 | False | 0.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_845' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_845', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-44' pid=540157 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23dd5bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4125s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.041597283 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,1,11} Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,1,16,1,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_121] | 1 | False | 0.25 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_121' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_121', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-41' pid=540247 parent=478383 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfc987c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.089174693 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,80,3,4} Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{80,80,3,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_426] | 1 | False | 0.17 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_426' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_426', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-40' pid=540458 parent=477818 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871218cf00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1508s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.093921506 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,22,9,11} Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,2,22,9,11} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_631] | 1 | False | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_631' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_631', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-41' pid=540549 parent=477988 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc84d450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_631/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_842] | 1 | False | 0.21 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_842' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_842', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-42' pid=540548 parent=478652 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9287b2e60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.123063359 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,11,1} Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,11,16,11,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_540] | 1 | False | 0.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_540' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_540', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-44' pid=540680 parent=478286 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ad30d80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.168346946 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,43,4} Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{12,4,30,43,4} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_904] | 1 | False | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_904' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_904', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=540656 parent=477734 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2e4b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.136550251 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{115,12} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{115,12} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_676] | 1 | False | 0.22 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_676' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_676', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-44' pid=540683 parent=478519 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8890810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_676/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_559] | 1 | False | 0.23 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_559' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_559', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=540682 parent=477887 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b274c0840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.253883701 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,43,12,30} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{4,4,43,12,30} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_469] | 1 | False | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_469' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_469', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=540725 parent=478084 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6830d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.198229305 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,11,9,2} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,11,9,2} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_343] | 1 | False | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_343' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_343', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -11 E assert -11 == 0 E + where -11 = <Process name='Process-47' pid=541377 parent=478387 stopped exitcode=-SIGSEGV>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40ef830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Reshape_343/artifacts/subgraph_0_tidl_net.bin | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_770] | 1 | False | 0.18 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_770' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_770', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-48' pid=541378 parent=477731 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f4dbf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.312543939 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1936,1,1} Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1936,1,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_918] | 1 | False | 0.17 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_918' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_918', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-46' pid=541551 parent=478427 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740ccaec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18677857 bytes MEM: Free's : 26 free's of 18677857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.394112788 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,6,5,1} Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{2,23,6,5,1} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1045] | 1 | False | 0.15 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_1045' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_1045', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=541662 parent=478585 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23cebe90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22572013 bytes MEM: Free's : 26 free's of 22572013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.370765186 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{224640} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{224640} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_826] | 1 | False | 0.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_826' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_826', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=541855 parent=477728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59392a7b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.432324210 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,11,16} Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{1,1,11,11,16} | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_441] | 1 | False | 0.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Reshape_441' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Reshape_441', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Reshape' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-43' pid=541898 parent=477744 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c2d8310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ 2025-05-07 00:35:22.440778358 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,2,11,9} Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 81, in run_inference return self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Reshape node. Name:'reshape_node' Status Message: /root/onnxruntime/onnxruntime/core/providers/cpu/tensor/reshape_helper.h:40 onnxruntime::ReshapeHelper::ReshapeHelper(const onnxruntime::TensorShape&, onnxruntime::TensorShapeVector&, bool) gsl::narrow_cast<int64_t>(input_shape.Size()) == size was false. The input tensor cannot be reshaped to the requested shape. Input shape:{}, requested shape:{11,22,2,11,9} | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_56] | 1 | True | 0.19 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27209fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.09 Core Time (ms) : 8.02 TIDL Subgraphs Processing Time (ms) : 7.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_984] | 1 | True | 0.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27dd3420 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16799s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.01 Core Time (ms) : 1.98 TIDL Subgraphs Processing Time (ms) : 1.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_764] | 1 | True | 0.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51fb3eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.45 Core Time (ms) : 7.42 TIDL Subgraphs Processing Time (ms) : 7.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_948] | 1 | True | 0.28 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfdac370 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_819] | 1 | True | 0.28 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a410a6f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1861s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1864s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.98 Core Time (ms) : 4.95 TIDL Subgraphs Processing Time (ms) : 4.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_930] | 1 | True | 0.30 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c3e8a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1970s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.82 Core Time (ms) : 17.80 TIDL Subgraphs Processing Time (ms) : 17.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_868] | 1 | True | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740ce2d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8871s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_58] | 1 | True | 0.15 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2720f300 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9867s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9870s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.07 Core Time (ms) : 0.96 TIDL Subgraphs Processing Time (ms) : 0.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_644] | 1 | True | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfdacf90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.78 Core Time (ms) : 23.79 TIDL Subgraphs Processing Time (ms) : 23.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_546] | 1 | True | 0.29 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27fb83d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1891s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.07 Core Time (ms) : 21.61 TIDL Subgraphs Processing Time (ms) : 21.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_393] | 1 | True | 0.20 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a97fb50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.50 Core Time (ms) : 1.39 TIDL Subgraphs Processing Time (ms) : 1.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_300] | 1 | True | 0.51 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272fb010 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.19 Core Time (ms) : 43.72 TIDL Subgraphs Processing Time (ms) : 43.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_242] | 1 | True | 0.42 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe74c4f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.60 Core Time (ms) : 62.35 TIDL Subgraphs Processing Time (ms) : 62.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_979] | 1 | True | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928825640 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.61 Core Time (ms) : 3.58 TIDL Subgraphs Processing Time (ms) : 3.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_26] | 1 | True | 0.35 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e429b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.46 Core Time (ms) : 2.42 TIDL Subgraphs Processing Time (ms) : 2.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_255] | 1 | True | 0.36 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122ee710 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2867s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.02 Core Time (ms) : 52.84 TIDL Subgraphs Processing Time (ms) : 52.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_419] | 1 | True | 0.30 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67ca340 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2221s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.20 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 1.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_499] | 1 | True | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8a0a6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.55 Core Time (ms) : 13.13 TIDL Subgraphs Processing Time (ms) : 13.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_552] | 1 | True | 0.29 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376c174560 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2032s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.52 Core Time (ms) : 6.03 TIDL Subgraphs Processing Time (ms) : 5.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_418] | 1 | True | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351aacf200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3305s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.10 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_937] | 1 | True | 0.23 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179bc1c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.84 Core Time (ms) : 9.81 TIDL Subgraphs Processing Time (ms) : 9.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_584] | 1 | True | 0.43 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc9cab30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.84 Core Time (ms) : 28.31 TIDL Subgraphs Processing Time (ms) : 28.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_666] | 1 | True | 0.26 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fb0480 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.04 Core Time (ms) : 8.42 TIDL Subgraphs Processing Time (ms) : 8.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_613] | 1 | True | 0.28 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8a0d420 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.05 Core Time (ms) : 8.66 TIDL Subgraphs Processing Time (ms) : 8.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_767] | 1 | True | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273015a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.36 Core Time (ms) : 3.34 TIDL Subgraphs Processing Time (ms) : 3.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_118] | 1 | True | 0.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35c37a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.15 Core Time (ms) : 9.01 TIDL Subgraphs Processing Time (ms) : 8.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_101] | 1 | True | 0.34 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f14ffc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3984s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.78 Core Time (ms) : 1.64 TIDL Subgraphs Processing Time (ms) : 1.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_475] | 1 | True | 0.39 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a987d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.89 Core Time (ms) : 59.75 TIDL Subgraphs Processing Time (ms) : 59.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1010] | 1 | True | 0.34 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c439290 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.28 Core Time (ms) : 10.26 TIDL Subgraphs Processing Time (ms) : 10.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_79] | 1 | True | 0.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740c409b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1615s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.84 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 1.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_111] | 1 | True | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bea8680 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.43 Core Time (ms) : 2.28 TIDL Subgraphs Processing Time (ms) : 2.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_294] | 1 | True | 0.35 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfdf5950 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.86 Core Time (ms) : 35.50 TIDL Subgraphs Processing Time (ms) : 35.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_827] | 1 | True | 0.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abbfa60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_645] | 1 | True | 0.28 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179baf80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.21 Core Time (ms) : 23.39 TIDL Subgraphs Processing Time (ms) : 23.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_531] | 1 | True | 0.24 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a196b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.05 Core Time (ms) : 26.64 TIDL Subgraphs Processing Time (ms) : 26.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_567] | 1 | True | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928a0f6f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1349s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.88 Core Time (ms) : 24.46 TIDL Subgraphs Processing Time (ms) : 24.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_445] | 1 | True | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8740f50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.09 Core Time (ms) : 5.00 TIDL Subgraphs Processing Time (ms) : 4.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_703] | 1 | True | 0.44 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d2cd40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 77.46 Core Time (ms) : 76.77 TIDL Subgraphs Processing Time (ms) : 76.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_414] | 1 | True | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582507fda680 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.30 Core Time (ms) : 4.21 TIDL Subgraphs Processing Time (ms) : 4.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_497] | 1 | True | 0.31 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f4211e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.08 Core Time (ms) : 18.48 TIDL Subgraphs Processing Time (ms) : 18.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_380] | 1 | True | 0.22 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a406a1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.05 Core Time (ms) : 0.96 TIDL Subgraphs Processing Time (ms) : 0.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_924] | 1 | True | 0.29 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7ec000 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.82 Core Time (ms) : 11.78 TIDL Subgraphs Processing Time (ms) : 11.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_759] | 1 | True | 0.40 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e452a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.98 Core Time (ms) : 83.99 TIDL Subgraphs Processing Time (ms) : 83.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_800] | 1 | True | 0.37 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68be000 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13567s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.70 Core Time (ms) : 2.68 TIDL Subgraphs Processing Time (ms) : 2.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_875] | 1 | True | 0.21 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179c2230 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19745s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.25 Core Time (ms) : 6.22 TIDL Subgraphs Processing Time (ms) : 6.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_857] | 1 | True | 0.23 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fb8f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2250s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.33 Core Time (ms) : 8.31 TIDL Subgraphs Processing Time (ms) : 8.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_715] | 1 | True | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92882d060 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14588s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.97 Core Time (ms) : 30.15 TIDL Subgraphs Processing Time (ms) : 30.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_408] | 1 | True | 0.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376beae480 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.23 Core Time (ms) : 14.12 TIDL Subgraphs Processing Time (ms) : 14.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_458] | 1 | True | 0.20 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8743130 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.72 Core Time (ms) : 3.62 TIDL Subgraphs Processing Time (ms) : 3.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_464] | 1 | True | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939222b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.86 Core Time (ms) : 4.76 TIDL Subgraphs Processing Time (ms) : 4.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_678] | 1 | True | 0.38 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080c6430 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.52 Core Time (ms) : 19.83 TIDL Subgraphs Processing Time (ms) : 19.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_780] | 1 | True | 0.24 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c43cef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.75 Core Time (ms) : 5.73 TIDL Subgraphs Processing Time (ms) : 5.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_305] | 1 | True | 0.26 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7eb4e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1863s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.97 Core Time (ms) : 34.93 TIDL Subgraphs Processing Time (ms) : 34.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_626] | 1 | True | 0.25 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17ba4730 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.69 Core Time (ms) : 11.25 TIDL Subgraphs Processing Time (ms) : 11.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_947] | 1 | True | 0.20 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa79350 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.61 Core Time (ms) : 1.59 TIDL Subgraphs Processing Time (ms) : 1.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_879] | 1 | True | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8833820 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2025s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.29 Core Time (ms) : 8.26 TIDL Subgraphs Processing Time (ms) : 8.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_544] | 1 | True | 0.23 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a19b4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.08 Core Time (ms) : 11.67 TIDL Subgraphs Processing Time (ms) : 11.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_46] | 1 | True | 0.34 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe75d150 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.87 Core Time (ms) : 26.83 TIDL Subgraphs Processing Time (ms) : 26.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_735] | 1 | True | 0.27 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e244d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.60 Core Time (ms) : 45.93 TIDL Subgraphs Processing Time (ms) : 45.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_374] | 1 | True | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d35caf30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.82 Core Time (ms) : 1.71 TIDL Subgraphs Processing Time (ms) : 1.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_838] | 1 | True | 0.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e4c7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.03 Core Time (ms) : 3.01 TIDL Subgraphs Processing Time (ms) : 2.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_710] | 1 | True | 0.26 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4159340 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.46 Core Time (ms) : 8.72 TIDL Subgraphs Processing Time (ms) : 8.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_830] | 1 | True | 0.30 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c43f1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.72 Core Time (ms) : 2.69 TIDL Subgraphs Processing Time (ms) : 2.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_334] | 1 | True | 0.46 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080c93c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 113.26 Core Time (ms) : 109.92 TIDL Subgraphs Processing Time (ms) : 109.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_312] | 1 | True | 0.26 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa78ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.46 Core Time (ms) : 31.23 TIDL Subgraphs Processing Time (ms) : 31.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_869] | 1 | True | 0.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8835ad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.33086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.33115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.33295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.33320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.33347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.33366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.33388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.33405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.33423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.33446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.33469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.33491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.33518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.33546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.33571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.33595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.33613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.33631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.33662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.33682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.33704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.33729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.33746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.33765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.33792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.33812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.33837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.33863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.33882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.33903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.33935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.33958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.33976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.34000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.34023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.34042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.34068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.34086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.34108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.34133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.34162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.34164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.34166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.40 Core Time (ms) : 7.36 TIDL Subgraphs Processing Time (ms) : 7.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_166] | 1 | True | 0.29 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f240f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20543s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.26 Core Time (ms) : 38.73 TIDL Subgraphs Processing Time (ms) : 38.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_9] | 1 | True | 0.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abc2730 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.473163216237587e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.12 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670345 bytes MEM: Free's : 26 free's of 18670345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_972] | 1 | True | 0.27 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe01990 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.25009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.25034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.25054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.25071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.25100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.25120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.25143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.25167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.25190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.59 Core Time (ms) : 0.57 TIDL Subgraphs Processing Time (ms) : 0.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_369] | 1 | True | 0.22 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59eceba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4006s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.07 Core Time (ms) : 6.98 TIDL Subgraphs Processing Time (ms) : 6.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_348] | 1 | True | 0.47 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3545c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 73.54 Core Time (ms) : 70.33 TIDL Subgraphs Processing Time (ms) : 70.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_701] | 1 | True | 0.22 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36b7110 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.08 Core Time (ms) : 31.45 TIDL Subgraphs Processing Time (ms) : 31.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_762] | 1 | True | 0.24 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e4e780 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.08 Core Time (ms) : 8.06 TIDL Subgraphs Processing Time (ms) : 8.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_104] | 1 | True | 0.23 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27261ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7170s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.72 Core Time (ms) : 2.60 TIDL Subgraphs Processing Time (ms) : 2.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_578] | 1 | True | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6aa2ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.17 Core Time (ms) : 13.55 TIDL Subgraphs Processing Time (ms) : 13.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_624] | 1 | True | 0.30 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376c181050 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.27 Core Time (ms) : 44.83 TIDL Subgraphs Processing Time (ms) : 44.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_899] | 1 | True | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa7d840 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.04 Core Time (ms) : 12.01 TIDL Subgraphs Processing Time (ms) : 11.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693277 bytes MEM: Free's : 26 free's of 18693277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_745] | 1 | True | 0.25 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fbaa00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.98 Core Time (ms) : 10.25 TIDL Subgraphs Processing Time (ms) : 10.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_161] | 1 | True | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c43c4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.44 Core Time (ms) : 7.93 TIDL Subgraphs Processing Time (ms) : 7.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23978093 bytes MEM: Free's : 26 free's of 23978093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_365] | 1 | True | 0.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f15a800 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.60 Core Time (ms) : 5.50 TIDL Subgraphs Processing Time (ms) : 5.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_110] | 1 | True | 0.45 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e87490d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.78 Core Time (ms) : 8.62 TIDL Subgraphs Processing Time (ms) : 8.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_143] | 1 | True | 0.22 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2734d700 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1654s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.20 Core Time (ms) : 4.80 TIDL Subgraphs Processing Time (ms) : 4.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_556] | 1 | True | 0.35 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187124e6ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.21 Core Time (ms) : 47.59 TIDL Subgraphs Processing Time (ms) : 47.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_431] | 1 | True | 0.34 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582507fe0e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.30 Core Time (ms) : 10.17 TIDL Subgraphs Processing Time (ms) : 10.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_107] | 1 | True | 0.28 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f19bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.97 Core Time (ms) : 20.83 TIDL Subgraphs Processing Time (ms) : 20.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_289] | 1 | True | 0.32 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4160400 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13821s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.92 Core Time (ms) : 43.22 TIDL Subgraphs Processing Time (ms) : 43.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_438] | 1 | True | 0.36 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67d6fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.37337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.37384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.37410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.37439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.37471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.37490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.37513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.37534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.37553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.37579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.37601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.37623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.37652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.37670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.37688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.37713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.37731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.37752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.37773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.37793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.37809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.37841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.37858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.37877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.37899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.37920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.37937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.37967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.37987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.38008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.38033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.38055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.38057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.38059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.41 Core Time (ms) : 1.29 TIDL Subgraphs Processing Time (ms) : 1.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_790] | 1 | True | 0.29 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde35a8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.28 Core Time (ms) : 31.26 TIDL Subgraphs Processing Time (ms) : 31.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_304] | 1 | True | 0.43 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fbd850 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.89 Core Time (ms) : 46.83 TIDL Subgraphs Processing Time (ms) : 46.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31051477 bytes MEM: Free's : 26 free's of 31051477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_674] | 1 | True | 0.31 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf9e4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.26071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.26100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.26119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.26133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.26153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.26166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.26180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.26253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.26268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.26285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.26297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.26310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.26328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.26340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.26351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.26370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.26382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.26397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.26410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.26422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.26434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.26451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.26467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.26479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.26494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.26506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.26521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.26538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.26554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.26566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.26587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.26600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.26618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.26635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.26650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.26665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.26687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.26689s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.26692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.92 Core Time (ms) : 17.31 TIDL Subgraphs Processing Time (ms) : 17.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_164] | 1 | True | 0.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f246480 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.35 Core Time (ms) : 33.81 TIDL Subgraphs Processing Time (ms) : 32.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_389] | 1 | True | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a992220 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.26 Core Time (ms) : 2.17 TIDL Subgraphs Processing Time (ms) : 2.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_721] | 1 | True | 0.24 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c43e530 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.96 Core Time (ms) : 24.22 TIDL Subgraphs Processing Time (ms) : 24.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_191] | 1 | True | 0.38 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27350e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.21 Core Time (ms) : 49.55 TIDL Subgraphs Processing Time (ms) : 49.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_711] | 1 | True | 0.22 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe763810 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.80 Core Time (ms) : 10.15 TIDL Subgraphs Processing Time (ms) : 10.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_709] | 1 | True | 0.32 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d35630 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.39 Core Time (ms) : 30.60 TIDL Subgraphs Processing Time (ms) : 30.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_580] | 1 | True | 0.47 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc9d6690 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.63 Core Time (ms) : 56.04 TIDL Subgraphs Processing Time (ms) : 55.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_490] | 1 | True | 0.17 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939230ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.23 Core Time (ms) : 1.14 TIDL Subgraphs Processing Time (ms) : 1.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_908] | 1 | True | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5200ab10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.14 Core Time (ms) : 4.12 TIDL Subgraphs Processing Time (ms) : 4.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_238] | 1 | True | 0.76 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8835e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 162.14 Core Time (ms) : 157.97 TIDL Subgraphs Processing Time (ms) : 157.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_206] | 1 | True | 0.32 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080cd730 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.47 Core Time (ms) : 36.52 TIDL Subgraphs Processing Time (ms) : 36.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_422] | 1 | True | 0.27 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde26e660 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.07 Core Time (ms) : 15.96 TIDL Subgraphs Processing Time (ms) : 15.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_831] | 1 | True | 0.27 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179d01e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.77 Core Time (ms) : 7.75 TIDL Subgraphs Processing Time (ms) : 7.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_919] | 1 | True | 0.42 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4165180 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.45056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.45090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.45119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.45143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.45168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.45192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.45213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.45232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.45256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.45277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.45300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.45323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.45342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.45365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.45389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.45411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.45433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.45456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.45478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.45502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.45520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.45542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.45562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.45585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.45604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.45626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.45644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.45661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.45683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.45702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.45725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.45744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.45762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.45781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.45803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.45820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.45845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.45884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.45909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.45932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.45958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.45960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.45962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.41 Core Time (ms) : 10.39 TIDL Subgraphs Processing Time (ms) : 10.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_855] | 1 | True | 0.36 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36c7e10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.05 Core Time (ms) : 13.03 TIDL Subgraphs Processing Time (ms) : 12.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_237] | 1 | True | 0.43 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68c37a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.64 Core Time (ms) : 52.51 TIDL Subgraphs Processing Time (ms) : 52.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_601] | 1 | True | 0.18 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe94ad10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.21 Core Time (ms) : 4.82 TIDL Subgraphs Processing Time (ms) : 4.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_81] | 1 | True | 0.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d66f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19912s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.89 Core Time (ms) : 20.80 TIDL Subgraphs Processing Time (ms) : 20.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_210] | 1 | True | 0.33 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e34ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.86 Core Time (ms) : 29.04 TIDL Subgraphs Processing Time (ms) : 28.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_93] | 1 | True | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f1e860 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5188s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.34 Core Time (ms) : 4.20 TIDL Subgraphs Processing Time (ms) : 4.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_287] | 1 | True | 0.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abd0f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.38 Core Time (ms) : 32.93 TIDL Subgraphs Processing Time (ms) : 32.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_833] | 1 | True | 0.22 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde35ece0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.96 Core Time (ms) : 7.94 TIDL Subgraphs Processing Time (ms) : 7.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_516] | 1 | True | 0.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f4301e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1923s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.99 Core Time (ms) : 13.57 TIDL Subgraphs Processing Time (ms) : 13.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_217] | 1 | True | 0.37 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712307f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 58.17 Core Time (ms) : 56.28 TIDL Subgraphs Processing Time (ms) : 56.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1013] | 1 | True | 0.22 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe0dfe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.14 Core Time (ms) : 2.11 TIDL Subgraphs Processing Time (ms) : 2.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1043] | 1 | True | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e70ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.845793752156807e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.36 Core Time (ms) : 11.30 TIDL Subgraphs Processing Time (ms) : 11.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18938701 bytes MEM: Free's : 26 free's of 18938701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_702] | 1 | True | 0.45 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7f43b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.15 Core Time (ms) : 20.50 TIDL Subgraphs Processing Time (ms) : 20.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_53] | 1 | True | 0.26 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa86cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_566] | 1 | True | 0.14 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928a20910 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.05 Core Time (ms) : 8.69 TIDL Subgraphs Processing Time (ms) : 8.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_637] | 1 | True | 0.35 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fc2b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.27 Core Time (ms) : 13.53 TIDL Subgraphs Processing Time (ms) : 13.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_761] | 1 | True | 0.30 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68c9100 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13165s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_306] | 1 | True | 0.24 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde35ccc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1705s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1707s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.00 Core Time (ms) : 12.92 TIDL Subgraphs Processing Time (ms) : 12.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_362] | 1 | True | 0.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351aae8c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.13 Core Time (ms) : 2.02 TIDL Subgraphs Processing Time (ms) : 1.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_887] | 1 | True | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe115a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.28 Core Time (ms) : 1.25 TIDL Subgraphs Processing Time (ms) : 1.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_803] | 1 | True | 0.18 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe76dad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1523s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.83 Core Time (ms) : 2.81 TIDL Subgraphs Processing Time (ms) : 2.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_47] | 1 | True | 0.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfafac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.34 Core Time (ms) : 6.32 TIDL Subgraphs Processing Time (ms) : 6.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_100] | 1 | True | 0.24 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a99a6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.19 Core Time (ms) : 2.06 TIDL Subgraphs Processing Time (ms) : 2.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_799] | 1 | True | 0.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36cd580 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.33 Core Time (ms) : 41.30 TIDL Subgraphs Processing Time (ms) : 41.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_205] | 1 | True | 0.40 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e55f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.03 Core Time (ms) : 39.99 TIDL Subgraphs Processing Time (ms) : 39.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_506] | 1 | True | 0.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff521f2b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.94 Core Time (ms) : 11.55 TIDL Subgraphs Processing Time (ms) : 11.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_119] | 1 | True | 0.28 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb178e89a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9188s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.86 Core Time (ms) : 11.74 TIDL Subgraphs Processing Time (ms) : 11.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_347] | 1 | True | 0.37 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939327880 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1419s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 125.44 Core Time (ms) : 121.74 TIDL Subgraphs Processing Time (ms) : 121.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_6] | 1 | True | 0.45 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe76be30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14800s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.059041461252587e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.19 Core Time (ms) : 14.16 TIDL Subgraphs Processing Time (ms) : 14.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670861 bytes MEM: Free's : 26 free's of 18670861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_128] | 1 | True | 0.35 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abd4bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.73 Core Time (ms) : 48.17 TIDL Subgraphs Processing Time (ms) : 48.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_798] | 1 | True | 0.12 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68cb650 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_12] | 1 | True | 0.30 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfaecb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13056s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.473163216237587e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.95 Core Time (ms) : 2.92 TIDL Subgraphs Processing Time (ms) : 2.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670345 bytes MEM: Free's : 26 free's of 18670345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_158] | 1 | True | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e3c3a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15993s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.61 Core Time (ms) : 9.14 TIDL Subgraphs Processing Time (ms) : 9.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_123] | 1 | True | 0.35 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871230cad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25025s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.23 Core Time (ms) : 9.80 TIDL Subgraphs Processing Time (ms) : 9.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_194] | 1 | True | 0.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52011700 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.00 Core Time (ms) : 17.52 TIDL Subgraphs Processing Time (ms) : 17.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_980] | 1 | True | 0.33 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9288491d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10018s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10019s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.10099s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.78 Core Time (ms) : 6.75 TIDL Subgraphs Processing Time (ms) : 6.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_322] | 1 | True | 0.26 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde361ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.68 Core Time (ms) : 37.39 TIDL Subgraphs Processing Time (ms) : 37.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_341] | 1 | True | 0.46 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179d5e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9828s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 90.19 Core Time (ms) : 86.98 TIDL Subgraphs Processing Time (ms) : 86.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_187] | 1 | True | 0.32 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c44e720 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2787s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.25 Core Time (ms) : 22.74 TIDL Subgraphs Processing Time (ms) : 22.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_222] | 1 | True | 0.44 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36cb1a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9535s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 76.64 Core Time (ms) : 74.97 TIDL Subgraphs Processing Time (ms) : 74.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_841] | 1 | True | 0.37 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080dcd00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.25985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.26049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.26077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.26110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.26145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.26169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.26197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.26314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.26336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.26366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.26386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.26408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.26433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.26455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.26481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.26505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.26525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.26584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.26609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.26632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.26654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.26677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.26702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.26724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.26744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.26767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.26796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.26818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.26839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.26861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.26886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.26908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.26937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.26962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.26987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.59 Core Time (ms) : 19.56 TIDL Subgraphs Processing Time (ms) : 19.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_373] | 1 | True | 0.38 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc7117d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1955s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.82 Core Time (ms) : 8.67 TIDL Subgraphs Processing Time (ms) : 8.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_609] | 1 | True | 0.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593950db20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13833s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.89 Core Time (ms) : 24.52 TIDL Subgraphs Processing Time (ms) : 24.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_512] | 1 | True | 0.66 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfff7a70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10748s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.91 Core Time (ms) : 35.38 TIDL Subgraphs Processing Time (ms) : 35.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_173] | 1 | True | 0.22 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a416fcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.66 Core Time (ms) : 37.13 TIDL Subgraphs Processing Time (ms) : 37.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_495] | 1 | True | 0.23 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6ab0170 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.58 Core Time (ms) : 10.20 TIDL Subgraphs Processing Time (ms) : 10.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_208] | 1 | True | 0.33 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff52013a10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2112s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.05 Core Time (ms) : 21.58 TIDL Subgraphs Processing Time (ms) : 21.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_699] | 1 | True | 0.15 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e883dea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1472s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.11 Core Time (ms) : 16.47 TIDL Subgraphs Processing Time (ms) : 16.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_153] | 1 | True | 0.46 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde362dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.19 Core Time (ms) : 53.53 TIDL Subgraphs Processing Time (ms) : 53.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_579] | 1 | True | 0.36 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187124f2c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3176s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.12 Core Time (ms) : 18.67 TIDL Subgraphs Processing Time (ms) : 18.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_704] | 1 | True | 0.21 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c451410 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.28 Core Time (ms) : 22.62 TIDL Subgraphs Processing Time (ms) : 22.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_124] | 1 | True | 0.34 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4173280 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.41 Core Time (ms) : 38.78 TIDL Subgraphs Processing Time (ms) : 38.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_3] | 1 | True | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abdac30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.204001024620725e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.22 Core Time (ms) : 4.20 TIDL Subgraphs Processing Time (ms) : 4.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670693 bytes MEM: Free's : 26 free's of 18670693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_999] | 1 | True | 0.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e5da20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.41 Core Time (ms) : 21.38 TIDL Subgraphs Processing Time (ms) : 21.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_326] | 1 | True | 0.38 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080db460 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3824s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.71 Core Time (ms) : 38.44 TIDL Subgraphs Processing Time (ms) : 38.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_165] | 1 | True | 0.31 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179d6fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.31 Core Time (ms) : 36.58 TIDL Subgraphs Processing Time (ms) : 36.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_938] | 1 | True | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e45720 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.99 Core Time (ms) : 9.97 TIDL Subgraphs Processing Time (ms) : 9.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_433] | 1 | True | 0.32 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c36ac30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.77 Core Time (ms) : 5.65 TIDL Subgraphs Processing Time (ms) : 5.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_381] | 1 | True | 0.23 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351aaf1f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1556s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.59 Core Time (ms) : 7.48 TIDL Subgraphs Processing Time (ms) : 7.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_717] | 1 | True | 0.43 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b273600b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.64 Core Time (ms) : 12.96 TIDL Subgraphs Processing Time (ms) : 12.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_993] | 1 | True | 0.30 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59393337c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.06 Core Time (ms) : 9.04 TIDL Subgraphs Processing Time (ms) : 9.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1001] | 1 | True | 0.20 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8848c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.19 Core Time (ms) : 3.16 TIDL Subgraphs Processing Time (ms) : 3.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_456] | 1 | True | 0.25 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc717be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.04 Core Time (ms) : 7.94 TIDL Subgraphs Processing Time (ms) : 7.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_481] | 1 | True | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a408b830 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.15 Core Time (ms) : 4.05 TIDL Subgraphs Processing Time (ms) : 4.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_400] | 1 | True | 0.22 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e67e95b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.21 Core Time (ms) : 1.12 TIDL Subgraphs Processing Time (ms) : 1.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_131] | 1 | True | 0.16 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e439f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.92 Core Time (ms) : 12.41 TIDL Subgraphs Processing Time (ms) : 12.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1014] | 1 | True | 0.19 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080e0560 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1003s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.34 Core Time (ms) : 5.31 TIDL Subgraphs Processing Time (ms) : 5.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_51] | 1 | True | 0.29 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe779100 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.15 Core Time (ms) : 4.13 TIDL Subgraphs Processing Time (ms) : 4.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_788] | 1 | True | 0.24 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abe25c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.7602s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.17 Core Time (ms) : 6.14 TIDL Subgraphs Processing Time (ms) : 6.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_76] | 1 | True | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f171180 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.87 Core Time (ms) : 0.80 TIDL Subgraphs Processing Time (ms) : 0.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_590] | 1 | True | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740f34ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.51 Core Time (ms) : 12.10 TIDL Subgraphs Processing Time (ms) : 12.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_874] | 1 | True | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e4b6f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.15 Core Time (ms) : 1.12 TIDL Subgraphs Processing Time (ms) : 1.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_598] | 1 | True | 0.44 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc9e8ce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.22 Core Time (ms) : 14.84 TIDL Subgraphs Processing Time (ms) : 14.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_662] | 1 | True | 0.34 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4176290 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.04 Core Time (ms) : 9.36 TIDL Subgraphs Processing Time (ms) : 9.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_501] | 1 | True | 0.31 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a1b9500 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.30 Core Time (ms) : 15.83 TIDL Subgraphs Processing Time (ms) : 15.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_367] | 1 | True | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376beced80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1764s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.36 Core Time (ms) : 1.26 TIDL Subgraphs Processing Time (ms) : 1.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_290] | 1 | True | 0.29 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe18290 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.50 Core Time (ms) : 36.01 TIDL Subgraphs Processing Time (ms) : 35.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_14] | 1 | True | 0.29 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa986d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.094976910130722e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.11 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18658291 bytes MEM: Free's : 26 free's of 18658291 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_335] | 1 | True | 0.64 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e884a6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17119s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 87.97 Core Time (ms) : 83.39 TIDL Subgraphs Processing Time (ms) : 83.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_961] | 1 | True | 0.22 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abe3f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.05 Core Time (ms) : 8.02 TIDL Subgraphs Processing Time (ms) : 7.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_606] | 1 | True | 0.31 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740f374c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.48 Core Time (ms) : 5.07 TIDL Subgraphs Processing Time (ms) : 5.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_201] | 1 | True | 0.67 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f25ccd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 101.74 Core Time (ms) : 99.22 TIDL Subgraphs Processing Time (ms) : 99.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35627117 bytes MEM: Free's : 26 free's of 35627117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_140] | 1 | True | 0.26 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c458280 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.27 Core Time (ms) : 7.83 TIDL Subgraphs Processing Time (ms) : 7.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_160] | 1 | True | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfbb510 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5697s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.97 Core Time (ms) : 12.40 TIDL Subgraphs Processing Time (ms) : 12.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_633] | 1 | True | 0.50 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde368d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 83.41 Core Time (ms) : 82.39 TIDL Subgraphs Processing Time (ms) : 82.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_773] | 1 | True | 0.23 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fdc720 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.30 Core Time (ms) : 29.27 TIDL Subgraphs Processing Time (ms) : 29.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693949 bytes MEM: Free's : 26 free's of 18693949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_962] | 1 | True | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a417cb90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.21 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_871] | 1 | True | 0.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e66bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.86 Core Time (ms) : 2.85 TIDL Subgraphs Processing Time (ms) : 2.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_75] | 1 | True | 0.46 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb178f4d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25186s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.97 Core Time (ms) : 16.85 TIDL Subgraphs Processing Time (ms) : 16.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_15] | 1 | True | 0.20 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe1aae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.094976910130722e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.66 Core Time (ms) : 9.63 TIDL Subgraphs Processing Time (ms) : 9.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672449 bytes MEM: Free's : 26 free's of 18672449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_514] | 1 | True | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523ac7e5f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.51 Core Time (ms) : 19.10 TIDL Subgraphs Processing Time (ms) : 19.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_796] | 1 | True | 0.29 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7805e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.73 Core Time (ms) : 13.70 TIDL Subgraphs Processing Time (ms) : 13.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_203] | 1 | True | 0.32 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c45ba90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.38 Core Time (ms) : 27.23 TIDL Subgraphs Processing Time (ms) : 27.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_658] | 1 | True | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e4ccc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5510s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.85 Core Time (ms) : 19.24 TIDL Subgraphs Processing Time (ms) : 19.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_250] | 1 | True | 0.43 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a417bd30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 98.64 Core Time (ms) : 93.55 TIDL Subgraphs Processing Time (ms) : 93.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_80] | 1 | True | 0.17 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59eefd30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.01 Core Time (ms) : 7.93 TIDL Subgraphs Processing Time (ms) : 7.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_513] | 1 | True | 0.32 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6abf480 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13837s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13839s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.70 Core Time (ms) : 34.08 TIDL Subgraphs Processing Time (ms) : 34.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_195] | 1 | True | 0.27 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080e4fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.07 Core Time (ms) : 11.52 TIDL Subgraphs Processing Time (ms) : 11.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35627117 bytes MEM: Free's : 26 free's of 35627117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_728] | 1 | True | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc80b370 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.43 Core Time (ms) : 14.82 TIDL Subgraphs Processing Time (ms) : 14.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_754] | 1 | True | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa9c800 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.56 Core Time (ms) : 24.89 TIDL Subgraphs Processing Time (ms) : 24.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_967] | 1 | True | 0.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abe7f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.19 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_581] | 1 | True | 0.30 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a1c06c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.04 Core Time (ms) : 13.53 TIDL Subgraphs Processing Time (ms) : 13.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_352] | 1 | True | 0.64 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfc0e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 250.78 Core Time (ms) : 246.62 TIDL Subgraphs Processing Time (ms) : 246.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_376] | 1 | True | 0.40 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27d65f50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.79 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19485289 bytes MEM: Free's : 26 free's of 19485289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_78] | 1 | True | 0.24 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8762da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1508s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.90 Core Time (ms) : 19.82 TIDL Subgraphs Processing Time (ms) : 19.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_834] | 1 | True | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92885ea10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.99 Core Time (ms) : 2.97 TIDL Subgraphs Processing Time (ms) : 2.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_862] | 1 | True | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc812a10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.92 Core Time (ms) : 1.90 TIDL Subgraphs Processing Time (ms) : 1.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_652] | 1 | True | 0.30 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179e0c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.17 Core Time (ms) : 15.49 TIDL Subgraphs Processing Time (ms) : 15.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_226] | 1 | True | 0.51 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e6a1e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5759s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 103.74 Core Time (ms) : 100.36 TIDL Subgraphs Processing Time (ms) : 100.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_946] | 1 | True | 0.28 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f262100 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.95 Core Time (ms) : 5.92 TIDL Subgraphs Processing Time (ms) : 5.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_291] | 1 | True | 0.40 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68dd6d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.168s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 84.37 Core Time (ms) : 82.52 TIDL Subgraphs Processing Time (ms) : 82.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_86] | 1 | True | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a9b4270 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6624s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.81 Core Time (ms) : 15.73 TIDL Subgraphs Processing Time (ms) : 15.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1017] | 1 | True | 0.24 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871231f3d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.92 Core Time (ms) : 5.90 TIDL Subgraphs Processing Time (ms) : 5.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_890] | 1 | True | 0.25 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e88537f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.39 Core Time (ms) : 3.37 TIDL Subgraphs Processing Time (ms) : 3.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_926] | 1 | True | 0.32 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36dde10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.22 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_302] | 1 | True | 0.25 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc811330 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.03 Core Time (ms) : 21.99 TIDL Subgraphs Processing Time (ms) : 21.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_872] | 1 | True | 0.26 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928860e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.02 Core Time (ms) : 10.00 TIDL Subgraphs Processing Time (ms) : 9.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_63] | 1 | True | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582507fff820 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.51 Core Time (ms) : 3.42 TIDL Subgraphs Processing Time (ms) : 3.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_209] | 1 | True | 0.56 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2736be90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 86.53 Core Time (ms) : 85.01 TIDL Subgraphs Processing Time (ms) : 84.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_716] | 1 | True | 0.38 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f260590 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.18 Core Time (ms) : 20.49 TIDL Subgraphs Processing Time (ms) : 20.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_944] | 1 | True | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3783a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.19 Core Time (ms) : 2.17 TIDL Subgraphs Processing Time (ms) : 2.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_229] | 1 | True | 0.90 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871231e180 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 213.54 Core Time (ms) : 205.13 TIDL Subgraphs Processing Time (ms) : 205.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_801] | 1 | True | 0.18 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aaa4bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1403s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.94 Core Time (ms) : 10.92 TIDL Subgraphs Processing Time (ms) : 10.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_41] | 1 | True | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d5e360 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.15 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_607] | 1 | True | 0.26 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825082d05d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6814s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.70 Core Time (ms) : 17.29 TIDL Subgraphs Processing Time (ms) : 17.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_420] | 1 | True | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e87671e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9026s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.03 Core Time (ms) : 1.93 TIDL Subgraphs Processing Time (ms) : 1.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_712] | 1 | True | 0.24 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68defe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.86 Core Time (ms) : 27.02 TIDL Subgraphs Processing Time (ms) : 26.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_360] | 1 | True | 0.46 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92885ee60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4816s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4818s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 119.34 Core Time (ms) : 116.24 TIDL Subgraphs Processing Time (ms) : 116.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_840] | 1 | True | 0.25 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179eb8f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.21 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_440] | 1 | True | 0.41 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bed94c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.80 Core Time (ms) : 15.67 TIDL Subgraphs Processing Time (ms) : 15.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_608] | 1 | True | 0.33 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03e000c910 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.30018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.30048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.30075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.30098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.30121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.30141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.30163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.30186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.30204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.30226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.30255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.30273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.30294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.30322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.30351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.30370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.30397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.30414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.30432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.30460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.30477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.30500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.30526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.30547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.30568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.30590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.30611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.30631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.30666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.30684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.30706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.30729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.30750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.30770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.30796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.30815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.30842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.30864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.30890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.30915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.30941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.30944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.30946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.50 Core Time (ms) : 32.64 TIDL Subgraphs Processing Time (ms) : 32.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_994] | 1 | True | 0.24 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939343290 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.29 Core Time (ms) : 6.27 TIDL Subgraphs Processing Time (ms) : 6.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_850] | 1 | True | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d60a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.36 Core Time (ms) : 1.34 TIDL Subgraphs Processing Time (ms) : 1.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_19] | 1 | True | 0.32 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e57070 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.747378468850379e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.24 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686669 bytes MEM: Free's : 26 free's of 18686669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_682] | 1 | True | 0.27 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c462d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.75 Core Time (ms) : 22.09 TIDL Subgraphs Processing Time (ms) : 22.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_718] | 1 | True | 0.28 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f2625c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.91 Core Time (ms) : 22.19 TIDL Subgraphs Processing Time (ms) : 22.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1042] | 1 | True | 0.29 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17a070b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.845793752156807e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.59 Core Time (ms) : 20.54 TIDL Subgraphs Processing Time (ms) : 20.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18938701 bytes MEM: Free's : 26 free's of 18938701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_915] | 1 | True | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc818470 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.15 Core Time (ms) : 1.13 TIDL Subgraphs Processing Time (ms) : 1.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_321] | 1 | True | 0.27 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36e0260 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.25 Core Time (ms) : 29.00 TIDL Subgraphs Processing Time (ms) : 28.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_698] | 1 | True | 0.33 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde37a070 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5201s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5204s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.81 Core Time (ms) : 18.15 TIDL Subgraphs Processing Time (ms) : 18.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_848] | 1 | True | 0.18 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe2ee60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.28 Core Time (ms) : 1.26 TIDL Subgraphs Processing Time (ms) : 1.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_392] | 1 | True | 0.27 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928776950 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.46 Core Time (ms) : 4.37 TIDL Subgraphs Processing Time (ms) : 4.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_976] | 1 | True | 0.25 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e885bcb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.26 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_147] | 1 | True | 0.43 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59fe9d90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.10 Core Time (ms) : 37.66 TIDL Subgraphs Processing Time (ms) : 37.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_911] | 1 | True | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080f40a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.23 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_909] | 1 | True | 0.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a418d6d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6217s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.27 Core Time (ms) : 3.25 TIDL Subgraphs Processing Time (ms) : 3.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_258] | 1 | True | 0.72 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939345fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 284.16 Core Time (ms) : 275.75 TIDL Subgraphs Processing Time (ms) : 275.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_148] | 1 | True | 0.24 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e733c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3128s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.12 Core Time (ms) : 5.62 TIDL Subgraphs Processing Time (ms) : 5.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_378] | 1 | True | 0.28 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272885a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.19 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 1.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_849] | 1 | True | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f26de30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.82 Core Time (ms) : 3.79 TIDL Subgraphs Processing Time (ms) : 3.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_932] | 1 | True | 0.19 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aaad0f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.72 Core Time (ms) : 10.70 TIDL Subgraphs Processing Time (ms) : 10.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_738] | 1 | True | 0.42 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825080f2660 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 69.37 Core Time (ms) : 68.38 TIDL Subgraphs Processing Time (ms) : 68.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_213] | 1 | True | 0.44 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928863020 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.27375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.27411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.27431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.27457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.27487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.27508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.27535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.27558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.27579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.27601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.27621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.28016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.28041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.28062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.28083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.28110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.28128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.28153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.28177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.28198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.28220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.28241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.28265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.28289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.28310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.28328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.28353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.28386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.28388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.28390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 87.29 Core Time (ms) : 84.93 TIDL Subgraphs Processing Time (ms) : 84.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_956] | 1 | True | 0.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc81d340 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2788s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.02 Core Time (ms) : 8.99 TIDL Subgraphs Processing Time (ms) : 8.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_417] | 1 | True | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8771140 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.35 Core Time (ms) : 2.26 TIDL Subgraphs Processing Time (ms) : 2.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_265] | 1 | True | 0.24 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68e7ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.54 Core Time (ms) : 29.10 TIDL Subgraphs Processing Time (ms) : 29.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_697] | 1 | True | 0.27 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe78b200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1745s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.45 Core Time (ms) : 20.78 TIDL Subgraphs Processing Time (ms) : 20.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_272] | 1 | True | 0.22 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a418c7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.49 Core Time (ms) : 24.09 TIDL Subgraphs Processing Time (ms) : 24.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_536] | 1 | True | 0.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae2405aac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.82 Core Time (ms) : 23.29 TIDL Subgraphs Processing Time (ms) : 23.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_589] | 1 | True | 0.23 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde560c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.09 Core Time (ms) : 12.69 TIDL Subgraphs Processing Time (ms) : 12.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_197] | 1 | True | 0.38 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351abf7c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.32 Core Time (ms) : 29.13 TIDL Subgraphs Processing Time (ms) : 29.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_987] | 1 | True | 0.35 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ff0730 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.01 Core Time (ms) : 2.99 TIDL Subgraphs Processing Time (ms) : 2.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_822] | 1 | True | 0.26 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c46df50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1396s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.32 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_805] | 1 | True | 0.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc8205e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.35 Core Time (ms) : 7.32 TIDL Subgraphs Processing Time (ms) : 7.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_970] | 1 | True | 0.23 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe31ac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.12 Core Time (ms) : 7.10 TIDL Subgraphs Processing Time (ms) : 7.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_368] | 1 | True | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe6a2f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1371s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.08 Core Time (ms) : 0.98 TIDL Subgraphs Processing Time (ms) : 0.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_5] | 1 | True | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a418e390 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.8140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.059041461252587e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.00 Core Time (ms) : 1.98 TIDL Subgraphs Processing Time (ms) : 1.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670861 bytes MEM: Free's : 26 free's of 18670861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_568] | 1 | True | 0.33 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712509e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20056s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.70 Core Time (ms) : 5.29 TIDL Subgraphs Processing Time (ms) : 5.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_40] | 1 | True | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5203a2b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.89 Core Time (ms) : 32.87 TIDL Subgraphs Processing Time (ms) : 32.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_276] | 1 | True | 0.35 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36eb180 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13054s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 58.92 Core Time (ms) : 57.35 TIDL Subgraphs Processing Time (ms) : 57.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_551] | 1 | True | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523ac923d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.56 Core Time (ms) : 31.16 TIDL Subgraphs Processing Time (ms) : 31.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_405] | 1 | True | 0.16 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23d8e550 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.10 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_385] | 1 | True | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250800bf00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.71 Core Time (ms) : 3.61 TIDL Subgraphs Processing Time (ms) : 3.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_375] | 1 | True | 0.21 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f185d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5643s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.69 Core Time (ms) : 3.60 TIDL Subgraphs Processing Time (ms) : 3.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_793] | 1 | True | 0.15 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9288692d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.08 Core Time (ms) : 2.06 TIDL Subgraphs Processing Time (ms) : 2.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1029] | 1 | True | 0.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfe5ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.845793752156807e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.78 Core Time (ms) : 4.74 TIDL Subgraphs Processing Time (ms) : 4.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18938701 bytes MEM: Free's : 26 free's of 18938701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_296] | 1 | True | 0.54 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e885dd20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 94.01 Core Time (ms) : 92.39 TIDL Subgraphs Processing Time (ms) : 92.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_931] | 1 | True | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41931b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5434s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.34 Core Time (ms) : 2.32 TIDL Subgraphs Processing Time (ms) : 2.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_965] | 1 | True | 0.36 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe792b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.04 Core Time (ms) : 8.01 TIDL Subgraphs Processing Time (ms) : 7.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_329] | 1 | True | 0.47 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68eb990 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10676s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 74.07 Core Time (ms) : 70.65 TIDL Subgraphs Processing Time (ms) : 70.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_602] | 1 | True | 0.34 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593952c060 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10028s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.86 Core Time (ms) : 26.43 TIDL Subgraphs Processing Time (ms) : 26.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_740] | 1 | True | 0.32 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928866470 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.31 Core Time (ms) : 34.60 TIDL Subgraphs Processing Time (ms) : 34.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_318] | 1 | True | 0.32 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aab0870 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.8088s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.12 Core Time (ms) : 36.91 TIDL Subgraphs Processing Time (ms) : 36.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_920] | 1 | True | 0.34 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde386510 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.69 Core Time (ms) : 11.66 TIDL Subgraphs Processing Time (ms) : 11.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_542] | 1 | True | 0.32 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871250c200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.36 Core Time (ms) : 29.94 TIDL Subgraphs Processing Time (ms) : 29.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_851] | 1 | True | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2737d660 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_936] | 1 | True | 0.31 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc825d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.73 Core Time (ms) : 2.71 TIDL Subgraphs Processing Time (ms) : 2.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_234] | 1 | True | 0.46 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe33e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 71.60 Core Time (ms) : 67.80 TIDL Subgraphs Processing Time (ms) : 67.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_463] | 1 | True | 0.24 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c3857c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.08 Core Time (ms) : 12.92 TIDL Subgraphs Processing Time (ms) : 12.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_474] | 1 | True | 0.20 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b272914e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1872s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1875s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.33 Core Time (ms) : 20.23 TIDL Subgraphs Processing Time (ms) : 20.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_823] | 1 | True | 0.25 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfd37d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2062s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.28 Core Time (ms) : 1.25 TIDL Subgraphs Processing Time (ms) : 1.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_902] | 1 | True | 0.32 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d6ed80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.31 Core Time (ms) : 3.29 TIDL Subgraphs Processing Time (ms) : 3.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_85] | 1 | True | 0.20 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a9c7d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.73 Core Time (ms) : 2.66 TIDL Subgraphs Processing Time (ms) : 2.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_636] | 1 | True | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe791000 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.90 Core Time (ms) : 44.09 TIDL Subgraphs Processing Time (ms) : 44.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_190] | 1 | True | 0.31 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36ec3f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.90 Core Time (ms) : 21.49 TIDL Subgraphs Processing Time (ms) : 19.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_35] | 1 | True | 0.33 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871232f2e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.172s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6754s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_30] | 1 | True | 0.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4199f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.31 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712293 bytes MEM: Free's : 26 free's of 18712293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_686] | 1 | True | 0.22 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc824150 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.39 Core Time (ms) : 13.74 TIDL Subgraphs Processing Time (ms) : 13.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_319] | 1 | True | 0.49 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68ee290 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2073s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 100.80 Core Time (ms) : 99.51 TIDL Subgraphs Processing Time (ms) : 99.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_942] | 1 | True | 0.19 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508100880 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.15 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_22] | 1 | True | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e87aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.27 Core Time (ms) : 3.25 TIDL Subgraphs Processing Time (ms) : 3.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1063] | 1 | True | 0.28 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92877fe30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003100822446872623 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.15 Core Time (ms) : 18.73 TIDL Subgraphs Processing Time (ms) : 18.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22810573 bytes MEM: Free's : 26 free's of 22810573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_685] | 1 | True | 0.31 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aab3a40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12371s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.50 Core Time (ms) : 22.81 TIDL Subgraphs Processing Time (ms) : 22.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_337] | 1 | True | 0.31 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe36200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1704s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.22 Core Time (ms) : 43.66 TIDL Subgraphs Processing Time (ms) : 43.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52025577 bytes MEM: Free's : 26 free's of 52025577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_450] | 1 | True | 0.39 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f0a390 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.40 Core Time (ms) : 16.30 TIDL Subgraphs Processing Time (ms) : 16.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_244] | 1 | True | 0.57 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc8271e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 119.53 Core Time (ms) : 116.20 TIDL Subgraphs Processing Time (ms) : 116.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_327] | 1 | True | 0.34 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff5203ed00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1867s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 64.10 Core Time (ms) : 60.77 TIDL Subgraphs Processing Time (ms) : 60.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_680] | 1 | True | 0.51 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c475f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 85.49 Core Time (ms) : 84.45 TIDL Subgraphs Processing Time (ms) : 84.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1016] | 1 | True | 0.47 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871232f4e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.66 Core Time (ms) : 15.63 TIDL Subgraphs Processing Time (ms) : 15.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_647] | 1 | True | 0.37 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f279c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.60 Core Time (ms) : 30.94 TIDL Subgraphs Processing Time (ms) : 30.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_141] | 1 | True | 0.32 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe793120 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.38 Core Time (ms) : 38.90 TIDL Subgraphs Processing Time (ms) : 38.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_784] | 1 | True | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e6dc90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1654s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_211] | 1 | True | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27382260 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 75.72 Core Time (ms) : 70.86 TIDL Subgraphs Processing Time (ms) : 70.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_72] | 1 | True | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740c86a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3283s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.69 Core Time (ms) : 9.63 TIDL Subgraphs Processing Time (ms) : 9.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_339] | 1 | True | 0.41 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8868a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 84.59 Core Time (ms) : 74.71 TIDL Subgraphs Processing Time (ms) : 74.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_971] | 1 | True | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508106bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.26 Core Time (ms) : 5.24 TIDL Subgraphs Processing Time (ms) : 5.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_622] | 1 | True | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03e001bdb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.16 Core Time (ms) : 31.72 TIDL Subgraphs Processing Time (ms) : 31.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_753] | 1 | True | 0.29 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68ef690 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.18 Core Time (ms) : 43.55 TIDL Subgraphs Processing Time (ms) : 43.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_582] | 1 | True | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939532c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.55 Core Time (ms) : 11.15 TIDL Subgraphs Processing Time (ms) : 11.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_281] | 1 | True | 0.35 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92886db70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.79 Core Time (ms) : 45.24 TIDL Subgraphs Processing Time (ms) : 45.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_897] | 1 | True | 0.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e6eb70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_372] | 1 | True | 0.36 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2a1940 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.27 Core Time (ms) : 1.16 TIDL Subgraphs Processing Time (ms) : 1.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_968] | 1 | True | 0.14 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ff9900 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_174] | 1 | True | 0.28 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfd6640 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.19 Core Time (ms) : 21.64 TIDL Subgraphs Processing Time (ms) : 21.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_748] | 1 | True | 0.38 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac06ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11990s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.38 Core Time (ms) : 45.41 TIDL Subgraphs Processing Time (ms) : 45.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_969] | 1 | True | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508109490 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.73 Core Time (ms) : 3.71 TIDL Subgraphs Processing Time (ms) : 3.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_654] | 1 | True | 0.42 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aab9500 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.175s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4771s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 90.88 Core Time (ms) : 90.07 TIDL Subgraphs Processing Time (ms) : 89.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_286] | 1 | True | 0.28 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59393510a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.09 Core Time (ms) : 25.51 TIDL Subgraphs Processing Time (ms) : 25.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_985] | 1 | True | 0.22 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e8c620 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.06 Core Time (ms) : 2.04 TIDL Subgraphs Processing Time (ms) : 2.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_447] | 1 | True | 0.23 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f0e2b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.144s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1580s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.12 Core Time (ms) : 4.02 TIDL Subgraphs Processing Time (ms) : 3.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_180] | 1 | True | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e6d260 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.45 Core Time (ms) : 13.95 TIDL Subgraphs Processing Time (ms) : 12.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_151] | 1 | True | 0.31 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17a037a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.5618s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.14 Core Time (ms) : 11.68 TIDL Subgraphs Processing Time (ms) : 11.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_692] | 1 | True | 0.48 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7990b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.29017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.29046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.29069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.29091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.29116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.29138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.29164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.29184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.29206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.29230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.29249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.29271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.29294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.29321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.29340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.29365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.29382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.29400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.29422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.29446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.29464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.29490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.29508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.29525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.29546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.29564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.29585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.29611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.29633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.29652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.29681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.29700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.29717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.29739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.29757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.29777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.29807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.29825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.29846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.29870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.29900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.29904s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.29907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.41 Core Time (ms) : 15.46 TIDL Subgraphs Processing Time (ms) : 15.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_836] | 1 | True | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e886fbe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.87 Core Time (ms) : 0.84 TIDL Subgraphs Processing Time (ms) : 0.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1019] | 1 | True | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfdc8c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_599] | 1 | True | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5825082ec940 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1664s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.06 Core Time (ms) : 4.67 TIDL Subgraphs Processing Time (ms) : 4.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_399] | 1 | True | 0.27 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928785200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.79 Core Time (ms) : 5.69 TIDL Subgraphs Processing Time (ms) : 5.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_690] | 1 | True | 0.35 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740d73cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.29 Core Time (ms) : 58.60 TIDL Subgraphs Processing Time (ms) : 58.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1021] | 1 | True | 0.24 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36fc0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.03 Core Time (ms) : 4.01 TIDL Subgraphs Processing Time (ms) : 3.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_585] | 1 | True | 0.24 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde5726c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.11 Core Time (ms) : 23.70 TIDL Subgraphs Processing Time (ms) : 23.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_867] | 1 | True | 0.21 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59ffeb00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.34 Core Time (ms) : 2.32 TIDL Subgraphs Processing Time (ms) : 2.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_202] | 1 | True | 0.32 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27388750 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.41 Core Time (ms) : 25.66 TIDL Subgraphs Processing Time (ms) : 25.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35627117 bytes MEM: Free's : 26 free's of 35627117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_565] | 1 | True | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d28054420 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.50 Core Time (ms) : 9.10 TIDL Subgraphs Processing Time (ms) : 9.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_632] | 1 | True | 0.19 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68f4ac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.33 Core Time (ms) : 19.63 TIDL Subgraphs Processing Time (ms) : 19.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_459] | 1 | True | 0.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc742d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.84 Core Time (ms) : 3.74 TIDL Subgraphs Processing Time (ms) : 3.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_271] | 1 | True | 0.47 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac0a180 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18125s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.00 Core Time (ms) : 49.91 TIDL Subgraphs Processing Time (ms) : 49.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1023] | 1 | True | 0.24 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250810e0b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.81 Core Time (ms) : 4.78 TIDL Subgraphs Processing Time (ms) : 4.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_257] | 1 | True | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68f7a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.64 Core Time (ms) : 37.38 TIDL Subgraphs Processing Time (ms) : 37.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_479] | 1 | True | 0.21 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f12320 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4945s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.33 Core Time (ms) : 1.23 TIDL Subgraphs Processing Time (ms) : 1.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_261] | 1 | True | 0.42 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b2738aaf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.25046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.25096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.25114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.25136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.25154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.25172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.25187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.25203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.25221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.25237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.25255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.25273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.25289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.25307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.25324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.25345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.25368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.25384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.25397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.25415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.25430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.25446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.25463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.25479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.25492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.25515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.25528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.25545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.25562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.25578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.30 Core Time (ms) : 51.52 TIDL Subgraphs Processing Time (ms) : 51.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_171] | 1 | True | 0.31 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe79ab90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.74 Core Time (ms) : 6.18 TIDL Subgraphs Processing Time (ms) : 6.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_467] | 1 | True | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e87867e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.51 Core Time (ms) : 11.42 TIDL Subgraphs Processing Time (ms) : 11.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_575] | 1 | True | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aca4e60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.64 Core Time (ms) : 5.20 TIDL Subgraphs Processing Time (ms) : 5.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_168] | 1 | True | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfde040 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.50 Core Time (ms) : 21.89 TIDL Subgraphs Processing Time (ms) : 21.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23978093 bytes MEM: Free's : 26 free's of 23978093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_691] | 1 | True | 0.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d36fc290 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17970s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.48 Core Time (ms) : 12.61 TIDL Subgraphs Processing Time (ms) : 12.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_900] | 1 | True | 0.36 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17a0d340 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.133s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.24 Core Time (ms) : 1.21 TIDL Subgraphs Processing Time (ms) : 1.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_726] | 1 | True | 0.21 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e68f88d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.98 Core Time (ms) : 20.29 TIDL Subgraphs Processing Time (ms) : 20.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1011] | 1 | True | 0.17 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593927da50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.02 Core Time (ms) : 10.99 TIDL Subgraphs Processing Time (ms) : 10.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_945] | 1 | True | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41a92d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_744] | 1 | True | 0.45 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c4813b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9118s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 117.89 Core Time (ms) : 116.92 TIDL Subgraphs Processing Time (ms) : 116.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_509] | 1 | True | 0.30 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871251dee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.81 Core Time (ms) : 42.34 TIDL Subgraphs Processing Time (ms) : 42.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_7] | 1 | True | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f71710 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.059041461252587e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.76 Core Time (ms) : 3.74 TIDL Subgraphs Processing Time (ms) : 3.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670861 bytes MEM: Free's : 26 free's of 18670861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_17] | 1 | True | 0.35 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc8335c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.747378468850379e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.77 Core Time (ms) : 10.74 TIDL Subgraphs Processing Time (ms) : 10.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686669 bytes MEM: Free's : 26 free's of 18686669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_708] | 1 | True | 0.26 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfe0340 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.34 Core Time (ms) : 19.66 TIDL Subgraphs Processing Time (ms) : 19.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_482] | 1 | True | 0.35 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f17630 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.26 Core Time (ms) : 1.17 TIDL Subgraphs Processing Time (ms) : 1.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_42] | 1 | True | 0.15 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f28af50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9778s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_60] | 1 | True | 0.24 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939192f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.70 Core Time (ms) : 4.63 TIDL Subgraphs Processing Time (ms) : 4.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_69] | 1 | True | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6810cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1535s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.80 Core Time (ms) : 3.73 TIDL Subgraphs Processing Time (ms) : 3.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_518] | 1 | True | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a438c3a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.69 Core Time (ms) : 7.27 TIDL Subgraphs Processing Time (ms) : 7.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_996] | 1 | True | 0.30 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3702640 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.11 Core Time (ms) : 2.09 TIDL Subgraphs Processing Time (ms) : 2.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_528] | 1 | True | 0.38 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe9817f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.76 Core Time (ms) : 16.28 TIDL Subgraphs Processing Time (ms) : 16.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_268] | 1 | True | 0.54 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27e760e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 74.18 Core Time (ms) : 69.07 TIDL Subgraphs Processing Time (ms) : 69.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_569] | 1 | True | 0.25 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27570c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.82 Core Time (ms) : 24.59 TIDL Subgraphs Processing Time (ms) : 24.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_313] | 1 | True | 0.26 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740c9ea30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.46 Core Time (ms) : 30.21 TIDL Subgraphs Processing Time (ms) : 28.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_989] | 1 | True | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac11d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_71] | 1 | True | 0.43 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23da7b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.29 Core Time (ms) : 8.21 TIDL Subgraphs Processing Time (ms) : 8.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_630] | 1 | True | 0.41 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187123398d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.40 Core Time (ms) : 9.73 TIDL Subgraphs Processing Time (ms) : 9.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_223] | 1 | True | 0.40 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde397530 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 109.82 Core Time (ms) : 108.35 TIDL Subgraphs Processing Time (ms) : 108.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36624077 bytes MEM: Free's : 26 free's of 36624077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_562] | 1 | True | 0.25 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6ae16f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1603s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.07 Core Time (ms) : 14.63 TIDL Subgraphs Processing Time (ms) : 14.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_112] | 1 | True | 0.37 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3617190 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20531s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.43 Core Time (ms) : 10.25 TIDL Subgraphs Processing Time (ms) : 10.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_670] | 1 | True | 0.30 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c928874c70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.15 Core Time (ms) : 48.47 TIDL Subgraphs Processing Time (ms) : 48.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_52] | 1 | True | 0.25 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c4878e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_747] | 1 | True | 0.45 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac107e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.17 Core Time (ms) : 42.16 TIDL Subgraphs Processing Time (ms) : 42.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_449] | 1 | True | 0.25 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e878c8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.86 Core Time (ms) : 2.77 TIDL Subgraphs Processing Time (ms) : 2.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_324] | 1 | True | 0.45 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe79f7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 79.84 Core Time (ms) : 78.25 TIDL Subgraphs Processing Time (ms) : 78.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_293] | 1 | True | 0.36 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740ca0940 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23136s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.67 Core Time (ms) : 45.55 TIDL Subgraphs Processing Time (ms) : 45.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_951] | 1 | True | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bfe9520 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.75 Core Time (ms) : 7.71 TIDL Subgraphs Processing Time (ms) : 7.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_638] | 1 | True | 0.27 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x633b27390c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.77 Core Time (ms) : 11.91 TIDL Subgraphs Processing Time (ms) : 11.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_521] | 1 | True | 0.25 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c6692e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5840s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5842s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.22 Core Time (ms) : 11.82 TIDL Subgraphs Processing Time (ms) : 10.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_646] | 1 | True | 0.25 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9288775b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.86 Core Time (ms) : 28.19 TIDL Subgraphs Processing Time (ms) : 28.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_779] | 1 | True | 0.31 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e887d0f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.22 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_74] | 1 | True | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2aefe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.85 Core Time (ms) : 4.75 TIDL Subgraphs Processing Time (ms) : 4.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_284] | 1 | True | 0.47 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc837b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.24 Core Time (ms) : 25.30 TIDL Subgraphs Processing Time (ms) : 25.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_298] | 1 | True | 0.30 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a008500 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.88 Core Time (ms) : 43.36 TIDL Subgraphs Processing Time (ms) : 43.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_523] | 1 | True | 0.23 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03e0032380 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.15 Core Time (ms) : 5.79 TIDL Subgraphs Processing Time (ms) : 5.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_283] | 1 | True | 0.35 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939288090 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.80 Core Time (ms) : 42.31 TIDL Subgraphs Processing Time (ms) : 42.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_295] | 1 | True | 0.48 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6903920 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.92 Core Time (ms) : 22.18 TIDL Subgraphs Processing Time (ms) : 22.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_629] | 1 | True | 0.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac124d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.30 Core Time (ms) : 21.59 TIDL Subgraphs Processing Time (ms) : 21.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_627] | 1 | True | 0.46 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c486400 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.58 Core Time (ms) : 16.90 TIDL Subgraphs Processing Time (ms) : 16.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_457] | 1 | True | 0.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2b1270 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.14 Core Time (ms) : 1.04 TIDL Subgraphs Processing Time (ms) : 1.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_269] | 1 | True | 0.23 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92887a320 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2477s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.64 Core Time (ms) : 26.94 TIDL Subgraphs Processing Time (ms) : 26.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33713047 bytes MEM: Free's : 26 free's of 33713047 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_247] | 1 | True | 0.54 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f291d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.85 Core Time (ms) : 48.57 TIDL Subgraphs Processing Time (ms) : 48.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_992] | 1 | True | 0.27 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e9bb70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.13 Core Time (ms) : 4.11 TIDL Subgraphs Processing Time (ms) : 4.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_10] | 1 | True | 0.24 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f7ec40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.473163216237587e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.80 Core Time (ms) : 5.77 TIDL Subgraphs Processing Time (ms) : 5.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670345 bytes MEM: Free's : 26 free's of 18670345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_525] | 1 | True | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376c1ce560 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9419s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.84 Core Time (ms) : 19.46 TIDL Subgraphs Processing Time (ms) : 19.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_427] | 1 | True | 0.44 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfd67a10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.42 Core Time (ms) : 9.32 TIDL Subgraphs Processing Time (ms) : 9.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_116] | 1 | True | 0.20 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f20420 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8513s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.71 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 1.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_67] | 1 | True | 0.18 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1784d170 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16682s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.85 Core Time (ms) : 2.79 TIDL Subgraphs Processing Time (ms) : 2.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_756] | 1 | True | 0.32 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740ca5e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.1131s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.1133s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1207s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3731s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.96 Core Time (ms) : 21.34 TIDL Subgraphs Processing Time (ms) : 21.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_724] | 1 | True | 0.48 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27da23a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.28369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.28410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.28441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.28461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.28480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.28502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.28520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.28547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.28566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.28588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.28610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.28629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.28648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.28675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.28696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.28718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.28740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.28766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.28767s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.28772s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.44 Core Time (ms) : 66.38 TIDL Subgraphs Processing Time (ms) : 66.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_448] | 1 | True | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a40c5450 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.94 Core Time (ms) : 1.85 TIDL Subgraphs Processing Time (ms) : 1.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_667] | 1 | True | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac14f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.06 Core Time (ms) : 15.41 TIDL Subgraphs Processing Time (ms) : 15.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_125] | 1 | True | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593928a410 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.44s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.45s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.95 Core Time (ms) : 9.47 TIDL Subgraphs Processing Time (ms) : 9.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_672] | 1 | True | 0.28 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc8385c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3753s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.30 Core Time (ms) : 19.59 TIDL Subgraphs Processing Time (ms) : 19.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_493] | 1 | True | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250802d7b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1419s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.86 Core Time (ms) : 4.76 TIDL Subgraphs Processing Time (ms) : 4.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_354] | 1 | True | 0.39 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f808a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.44 Core Time (ms) : 52.52 TIDL Subgraphs Processing Time (ms) : 52.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_935] | 1 | True | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e9e350 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6041s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.49 Core Time (ms) : 8.46 TIDL Subgraphs Processing Time (ms) : 8.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_847] | 1 | True | 0.13 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6909720 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.22 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_169] | 1 | True | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde3a0900 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.53 Core Time (ms) : 17.01 TIDL Subgraphs Processing Time (ms) : 16.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_106] | 1 | True | 0.25 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187122583b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.36 Core Time (ms) : 4.23 TIDL Subgraphs Processing Time (ms) : 3.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_436] | 1 | True | 0.37 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c39ed40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.04 Core Time (ms) : 20.89 TIDL Subgraphs Processing Time (ms) : 20.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_176] | 1 | True | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41b10b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.75 Core Time (ms) : 7.26 TIDL Subgraphs Processing Time (ms) : 7.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_487] | 1 | True | 0.37 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59391a1eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.09 Core Time (ms) : 1.00 TIDL Subgraphs Processing Time (ms) : 0.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_817] | 1 | True | 0.31 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7a8b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.77 Core Time (ms) : 2.74 TIDL Subgraphs Processing Time (ms) : 2.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_16] | 1 | True | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac17980 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.094976910130722e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.97 Core Time (ms) : 15.95 TIDL Subgraphs Processing Time (ms) : 15.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672449 bytes MEM: Free's : 26 free's of 18672449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_782] | 1 | True | 0.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250811e430 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.15 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_861] | 1 | True | 0.33 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfe56c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.71 Core Time (ms) : 28.68 TIDL Subgraphs Processing Time (ms) : 28.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_84] | 1 | True | 0.27 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde2b9140 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.93 Core Time (ms) : 6.86 TIDL Subgraphs Processing Time (ms) : 6.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_349] | 1 | True | 0.86 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c92887dc60 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 71.10 Core Time (ms) : 66.61 TIDL Subgraphs Processing Time (ms) : 66.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_543] | 1 | True | 0.44 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f477620 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.15 Core Time (ms) : 50.56 TIDL Subgraphs Processing Time (ms) : 50.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_379] | 1 | True | 0.44 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf02490 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.35 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 1.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_264] | 1 | True | 0.36 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a010440 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.156s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.25016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.25038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.44 Core Time (ms) : 17.80 TIDL Subgraphs Processing Time (ms) : 17.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_37] | 1 | True | 0.28 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17940940 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.99 Core Time (ms) : 1.97 TIDL Subgraphs Processing Time (ms) : 1.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_953] | 1 | True | 0.23 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6187123486a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_178] | 1 | True | 0.35 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23e9e080 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.77 Core Time (ms) : 6.27 TIDL Subgraphs Processing Time (ms) : 6.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_577] | 1 | True | 0.36 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27f89f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.95 Core Time (ms) : 27.56 TIDL Subgraphs Processing Time (ms) : 27.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_503] | 1 | True | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a4398100 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.23 Core Time (ms) : 10.84 TIDL Subgraphs Processing Time (ms) : 10.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_13] | 1 | True | 0.18 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f82b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.094976910130722e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.06 Core Time (ms) : 4.04 TIDL Subgraphs Processing Time (ms) : 4.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672449 bytes MEM: Free's : 26 free's of 18672449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_183] | 1 | True | 0.19 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58250811b200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.48 Core Time (ms) : 8.02 TIDL Subgraphs Processing Time (ms) : 7.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_700] | 1 | True | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e690b200 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.61 Core Time (ms) : 20.81 TIDL Subgraphs Processing Time (ms) : 20.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_355] | 1 | True | 0.78 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c48b650 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 244.38 Core Time (ms) : 240.02 TIDL Subgraphs Processing Time (ms) : 239.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_288] | 1 | True | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ac196e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 79.02 Core Time (ms) : 75.57 TIDL Subgraphs Processing Time (ms) : 75.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_248] | 1 | True | 0.70 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a593928edc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 225.70 Core Time (ms) : 199.36 TIDL Subgraphs Processing Time (ms) : 199.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_669] | 1 | True | 0.33 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41b5b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1682s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.03 Core Time (ms) : 27.37 TIDL Subgraphs Processing Time (ms) : 27.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_435] | 1 | True | 0.33 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a9e8870 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.85 Core Time (ms) : 5.73 TIDL Subgraphs Processing Time (ms) : 5.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_266] | 1 | True | 0.41 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1793f5d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 88.16 Core Time (ms) : 82.74 TIDL Subgraphs Processing Time (ms) : 82.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_595] | 1 | True | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740e93710 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.86 Core Time (ms) : 15.48 TIDL Subgraphs Processing Time (ms) : 15.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_494] | 1 | True | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae24083530 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12580s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.32 Core Time (ms) : 7.87 TIDL Subgraphs Processing Time (ms) : 7.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_49] | 1 | True | 0.33 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f299840 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.21 Core Time (ms) : 17.18 TIDL Subgraphs Processing Time (ms) : 17.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_664] | 1 | True | 0.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8881260 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.40 Core Time (ms) : 42.41 TIDL Subgraphs Processing Time (ms) : 42.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_432] | 1 | True | 0.21 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f2a100 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5417s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.55 Core Time (ms) : 4.46 TIDL Subgraphs Processing Time (ms) : 4.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_412] | 1 | True | 0.19 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51e9d600 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1773s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.10 Core Time (ms) : 1.00 TIDL Subgraphs Processing Time (ms) : 0.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_437] | 1 | True | 0.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740bc75b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.92 Core Time (ms) : 3.81 TIDL Subgraphs Processing Time (ms) : 3.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_928] | 1 | True | 0.26 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871234a550 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.46 Core Time (ms) : 6.44 TIDL Subgraphs Processing Time (ms) : 6.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_394] | 1 | True | 0.22 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3540500 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6084s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.47 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 1.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_145] | 1 | True | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a15a41b8010 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.91 Core Time (ms) : 12.46 TIDL Subgraphs Processing Time (ms) : 12.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_91] | 1 | True | 0.17 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523a9ea6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.54 Core Time (ms) : 4.41 TIDL Subgraphs Processing Time (ms) : 4.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20126413 bytes MEM: Free's : 26 free's of 20126413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_309] | 1 | True | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27dad0a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.54 Core Time (ms) : 19.37 TIDL Subgraphs Processing Time (ms) : 19.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_39] | 1 | True | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe7acc90 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.2853s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.98 Core Time (ms) : 20.94 TIDL Subgraphs Processing Time (ms) : 20.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_454] | 1 | True | 0.20 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23db71a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.94 Core Time (ms) : 7.85 TIDL Subgraphs Processing Time (ms) : 7.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_310] | 1 | True | 0.38 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f8a530 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.32 Core Time (ms) : 24.13 TIDL Subgraphs Processing Time (ms) : 24.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_934] | 1 | True | 0.32 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc8452f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.26494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.26527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.26621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.26652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.26678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.26698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.26721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.26828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.26852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.26882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.26905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.26926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.26947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.26966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.26990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27572s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.86 Core Time (ms) : 5.83 TIDL Subgraphs Processing Time (ms) : 5.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_950] | 1 | True | 0.22 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17944860 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.85 Core Time (ms) : 20.83 TIDL Subgraphs Processing Time (ms) : 20.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_177] | 1 | True | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x64c740cb31b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.64 Core Time (ms) : 14.16 TIDL Subgraphs Processing Time (ms) : 14.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_889] | 1 | True | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f29b910 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.15 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_597] | 1 | True | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8a68a00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.765s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.36 Core Time (ms) : 9.93 TIDL Subgraphs Processing Time (ms) : 9.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_623] | 1 | True | 0.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3810850 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.09 Core Time (ms) : 36.67 TIDL Subgraphs Processing Time (ms) : 36.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_156] | 1 | True | 0.28 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508045a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.80 Core Time (ms) : 5.37 TIDL Subgraphs Processing Time (ms) : 5.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_878] | 1 | True | 0.39 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61871234db00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.21 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_555] | 1 | True | 0.29 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae24088820 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.51 Core Time (ms) : 28.12 TIDL Subgraphs Processing Time (ms) : 28.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_683] | 1 | True | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27daea80 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.38 Core Time (ms) : 38.71 TIDL Subgraphs Processing Time (ms) : 38.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_142] | 1 | True | 0.22 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb179428f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.56 Core Time (ms) : 10.11 TIDL Subgraphs Processing Time (ms) : 10.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_988] | 1 | True | 0.15 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf1a1c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4721s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4723s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_434] | 1 | True | 0.28 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59f2feb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.97 Core Time (ms) : 9.82 TIDL Subgraphs Processing Time (ms) : 9.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1002] | 1 | True | 0.29 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a5939296340 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.76 Core Time (ms) : 12.73 TIDL Subgraphs Processing Time (ms) : 12.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_477] | 1 | True | 0.31 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582507f5ded0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.15120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17094s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.77 Core Time (ms) : 25.63 TIDL Subgraphs Processing Time (ms) : 25.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_253] | 1 | True | 0.54 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf19e10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 109.43 Core Time (ms) : 101.99 TIDL Subgraphs Processing Time (ms) : 101.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54173719 bytes MEM: Free's : 26 free's of 54173719 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_508] | 1 | True | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x631fde4b7400 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.70 Core Time (ms) : 6.31 TIDL Subgraphs Processing Time (ms) : 6.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_641] | 1 | True | 0.23 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e690f700 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.12 Core Time (ms) : 14.38 TIDL Subgraphs Processing Time (ms) : 14.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_353] | 1 | True | 0.57 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6520e8888540 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.16 Core Time (ms) : 65.06 TIDL Subgraphs Processing Time (ms) : 64.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_442] | 1 | True | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27cc71e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.32 Core Time (ms) : 1.23 TIDL Subgraphs Processing Time (ms) : 1.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_507] | 1 | True | 0.21 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f5a200ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.67 Core Time (ms) : 5.24 TIDL Subgraphs Processing Time (ms) : 5.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23111533 bytes MEM: Free's : 26 free's of 23111533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_576] | 1 | True | 0.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523abe3510 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.96 Core Time (ms) : 12.54 TIDL Subgraphs Processing Time (ms) : 12.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_734] | 1 | True | 0.26 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62ae23ea6640 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.64 Core Time (ms) : 17.89 TIDL Subgraphs Processing Time (ms) : 17.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_657] | 1 | True | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57a6e6911740 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.14 Core Time (ms) : 48.28 TIDL Subgraphs Processing Time (ms) : 48.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_332] | 1 | True | 0.58 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3632c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1574s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 130.10 Core Time (ms) : 123.88 TIDL Subgraphs Processing Time (ms) : 123.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_27] | 1 | True | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1794e100 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.37 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_587] | 1 | True | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523abe55e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6969s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.05 Core Time (ms) : 13.60 TIDL Subgraphs Processing Time (ms) : 13.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_317] | 1 | True | 0.33 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dc81c494a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.49 Core Time (ms) : 16.29 TIDL Subgraphs Processing Time (ms) : 16.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31767181 bytes MEM: Free's : 26 free's of 31767181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_620] | 1 | True | 0.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb17b30700 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20073s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.61 Core Time (ms) : 39.07 TIDL Subgraphs Processing Time (ms) : 39.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_185] | 1 | True | 0.29 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf1aa00 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.92 Core Time (ms) : 13.39 TIDL Subgraphs Processing Time (ms) : 13.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_816] | 1 | True | 0.30 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51f95b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.42292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.42335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.42359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.42388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.42417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.42437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.42457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.42478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.42505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.42528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.42557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.42581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.42601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.42626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.42648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.42667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.42685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.42707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.42728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.42752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.42774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.42795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.42817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.42839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.42873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.42895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.42922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.42945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.42965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.42988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.43014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.43032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.43057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.43076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.43093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.43118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.43141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.43160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.43181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.43202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.43228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.43230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.43233s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.20 Core Time (ms) : 5.18 TIDL Subgraphs Processing Time (ms) : 5.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_401] | 1 | True | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27ccc670 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.26 Core Time (ms) : 27.16 TIDL Subgraphs Processing Time (ms) : 27.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_99] | 1 | True | 0.24 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dfc931d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.76 Core Time (ms) : 11.63 TIDL Subgraphs Processing Time (ms) : 11.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20035693 bytes MEM: Free's : 26 free's of 20035693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_649] | 1 | True | 0.23 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60c9287a7cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.38 Core Time (ms) : 40.74 TIDL Subgraphs Processing Time (ms) : 40.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_665] | 1 | True | 0.27 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712271700 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13584s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.24 Core Time (ms) : 18.57 TIDL Subgraphs Processing Time (ms) : 18.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_492] | 1 | True | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6389bc761940 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.33 Core Time (ms) : 15.21 TIDL Subgraphs Processing Time (ms) : 15.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_172] | 1 | True | 0.37 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60351ab499b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.53 Core Time (ms) : 19.97 TIDL Subgraphs Processing Time (ms) : 19.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24299213 bytes MEM: Free's : 26 free's of 24299213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_619] | 1 | True | 0.38 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe8b5c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.26 Core Time (ms) : 21.69 TIDL Subgraphs Processing Time (ms) : 21.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1] | 1 | True | 0.21 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf1dd30 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.204001024620725e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.07 Core Time (ms) : 3.14 TIDL Subgraphs Processing Time (ms) : 3.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18670693 bytes MEM: Free's : 26 free's of 18670693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_929] | 1 | True | 0.24 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x618712278bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.23 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_502] | 1 | True | 0.25 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d3818f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.76 Core Time (ms) : 21.25 TIDL Subgraphs Processing Time (ms) : 21.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_974] | 1 | True | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f1ca180 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.65 Core Time (ms) : 15.62 TIDL Subgraphs Processing Time (ms) : 15.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_144] | 1 | True | 0.36 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa06bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.41 Core Time (ms) : 14.89 TIDL Subgraphs Processing Time (ms) : 14.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23516877 bytes MEM: Free's : 26 free's of 23516877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_82] | 1 | True | 0.27 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614f59e5d870 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.89 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19322573 bytes MEM: Free's : 26 free's of 19322573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_359] | 1 | True | 0.37 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf1f930 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.18 Core Time (ms) : 35.92 TIDL Subgraphs Processing Time (ms) : 35.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_398] | 1 | True | 0.30 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a59391b6440 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.16123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.59 Core Time (ms) : 5.47 TIDL Subgraphs Processing Time (ms) : 5.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_1015] | 1 | True | 0.32 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x582508058570 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.32047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.32081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.32114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.32136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.32166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.32188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.32213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.32237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.32260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.32282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.32308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.32328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.32346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.32377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.32401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.32425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.32448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.32468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.32495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.32518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.32543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.32570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.32592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.32615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.32634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.32655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.32681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.32702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.32720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.32744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.32768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.32788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.32812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.32831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.32853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.32875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.32900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.32919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.32944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.32965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.32989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.32991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.32993s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.07 Core Time (ms) : 4.04 TIDL Subgraphs Processing Time (ms) : 4.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_413] | 1 | True | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bff51eabf10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.82 Core Time (ms) : 13.72 TIDL Subgraphs Processing Time (ms) : 13.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_406] | 1 | True | 0.27 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x57c4d354ca10 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5513s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000308430408252761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.93 Core Time (ms) : 12.82 TIDL Subgraphs Processing Time (ms) : 12.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19547125 bytes MEM: Free's : 26 free's of 19547125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_983] | 1 | True | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x619d27dc43f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.67573655754685e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.76 Core Time (ms) : 10.72 TIDL Subgraphs Processing Time (ms) : 10.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693157 bytes MEM: Free's : 26 free's of 18693157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_267] | 1 | True | 0.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a8d1f1c8e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1757s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.41 Core Time (ms) : 34.88 TIDL Subgraphs Processing Time (ms) : 34.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34590265 bytes MEM: Free's : 26 free's of 34590265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_675] | 1 | True | 0.25 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5abffe6d2e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031008085399367874 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.10 Core Time (ms) : 28.43 TIDL Subgraphs Processing Time (ms) : 28.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27094093 bytes MEM: Free's : 26 free's of 27094093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_357] | 1 | True | 0.34 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5feb1794fcc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.55 Core Time (ms) : 64.82 TIDL Subgraphs Processing Time (ms) : 64.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53961461 bytes MEM: Free's : 26 free's of 53961461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_856] | 1 | True | 0.15 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61523aa0e1a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.88454037066141e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.24 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18709805 bytes MEM: Free's : 26 free's of 18709805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_522] | 1 | True | 0.17 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a03dff6c190 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6728s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310103116234044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.09 Core Time (ms) : 4.67 TIDL Subgraphs Processing Time (ms) : 4.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23373133 bytes MEM: Free's : 26 free's of 23373133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Reshape_28] | 1 | True | 0.12 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5a376bf27c70 Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.04 Core Time (ms) : 7.01 TIDL Subgraphs Processing Time (ms) : 6.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712269 bytes MEM: Free's : 26 free's of 18712269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||